const (
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
F30
F31
V0 // VSX extension, F0 is V0[0:63].
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31
VS0
VS1
VS2
VS3
VS4
VS5
VS6
VS7
VS8
VS9
VS10
VS11
VS12
VS13
VS14
VS15
VS16
VS17
VS18
VS19
VS20
VS21
VS22
VS23
VS24
VS25
VS26
VS27
VS28
VS29
VS30
VS31
VS32
VS33
VS34
VS35
VS36
VS37
VS38
VS39
VS40
VS41
VS42
VS43
VS44
VS45
VS46
VS47
VS48
VS49
VS50
VS51
VS52
VS53
VS54
VS55
VS56
VS57
VS58
VS59
VS60
VS61
VS62
VS63
)
const (
// Condition Regster bits
Cond0LT
Cond0GT
Cond0EQ
Cond0SO
Cond1LT
Cond1GT
Cond1EQ
Cond1SO
Cond2LT
Cond2GT
Cond2EQ
Cond2SO
Cond3LT
Cond3GT
Cond3EQ
Cond3SO
Cond4LT
Cond4GT
Cond4EQ
Cond4SO
Cond5LT
Cond5GT
Cond5EQ
Cond5SO
Cond6LT
Cond6GT
Cond6EQ
Cond6SO
Cond7LT
Cond7GT
Cond7EQ
Cond7SO
// Condition Register Fields
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
)
const (
CNTLZW
CNTLZWCC
B
BA
BL
BLA
BC
BCA
BCL
BCLA
BCLR
BCLRL
BCCTR
BCCTRL
BCTAR
BCTARL
CRAND
CROR
CRNAND
CRXOR
CRNOR
CRANDC
MCRF
CREQV
CRORC
SC
CLRBHRB
MFBHRBE
LBZ
LBZU
LBZX
LBZUX
LHZ
LHZU
LHZX
LHZUX
LHA
LHAU
LHAX
LHAUX
LWZ
LWZU
LWZX
LWZUX
LWA
LWAX
LWAUX
LD
LDU
LDX
LDUX
STB
STBU
STBX
STBUX
STH
STHU
STHX
STHUX
STW
STWU
STWX
STWUX
STD
STDU
STDX
STDUX
LQ
STQ
LHBRX
LWBRX
STHBRX
STWBRX
LDBRX
STDBRX
LMW
STMW
LSWI
LSWX
STSWI
STSWX
LI
ADDI
LIS
ADDIS
ADD
ADDCC
ADDO
ADDOCC
ADDIC
SUBF
SUBFCC
SUBFO
SUBFOCC
ADDICCC
SUBFIC
ADDC
ADDCCC
ADDCO
ADDCOCC
SUBFC
SUBFCCC
SUBFCO
SUBFCOCC
ADDE
ADDECC
ADDEO
ADDEOCC
ADDME
ADDMECC
ADDMEO
ADDMEOCC
SUBFE
SUBFECC
SUBFEO
SUBFEOCC
SUBFME
SUBFMECC
SUBFMEO
SUBFMEOCC
ADDZE
ADDZECC
ADDZEO
ADDZEOCC
SUBFZE
SUBFZECC
SUBFZEO
SUBFZEOCC
NEG
NEGCC
NEGO
NEGOCC
MULLI
MULLW
MULLWCC
MULLWO
MULLWOCC
MULHW
MULHWCC
MULHWU
MULHWUCC
DIVW
DIVWCC
DIVWO
DIVWOCC
DIVWU
DIVWUCC
DIVWUO
DIVWUOCC
DIVWE
DIVWECC
DIVWEO
DIVWEOCC
DIVWEU
DIVWEUCC
DIVWEUO
DIVWEUOCC
MULLD
MULLDCC
MULLDO
MULLDOCC
MULHDU
MULHDUCC
MULHD
MULHDCC
DIVD
DIVDCC
DIVDO
DIVDOCC
DIVDU
DIVDUCC
DIVDUO
DIVDUOCC
DIVDE
DIVDECC
DIVDEO
DIVDEOCC
DIVDEU
DIVDEUCC
DIVDEUO
DIVDEUOCC
CMPWI
CMPDI
CMPW
CMPD
CMPLWI
CMPLDI
CMPLW
CMPLD
TWI
TW
TDI
ISEL
TD
ANDICC
ANDISCC
ORI
ORIS
XORI
XORIS
AND
ANDCC
XOR
XORCC
NAND
NANDCC
OR
ORCC
NOR
NORCC
ANDC
ANDCCC
EXTSB
EXTSBCC
EQV
EQVCC
ORC
ORCCC
EXTSH
EXTSHCC
CMPB
POPCNTB
POPCNTW
PRTYD
PRTYW
EXTSW
EXTSWCC
CNTLZD
CNTLZDCC
POPCNTD
BPERMD
RLWINM
RLWINMCC
RLWNM
RLWNMCC
RLWIMI
RLWIMICC
RLDICL
RLDICLCC
RLDICR
RLDICRCC
RLDIC
RLDICCC
RLDCL
RLDCLCC
RLDCR
RLDCRCC
RLDIMI
RLDIMICC
SLW
SLWCC
SRW
SRWCC
SRAWI
SRAWICC
SRAW
SRAWCC
SLD
SLDCC
SRD
SRDCC
SRADI
SRADICC
SRAD
SRADCC
CDTBCD
CBCDTD
ADDG6S
MTSPR
MFSPR
MTCRF
MFCR
MTSLE
MFVSRD
MFVSRWZ
MTVSRD
MTVSRWA
MTVSRWZ
MTOCRF
MFOCRF
MCRXR
MTDCRUX
MFDCRUX
LFS
LFSU
LFSX
LFSUX
LFD
LFDU
LFDX
LFDUX
LFIWAX
LFIWZX
STFS
STFSU
STFSX
STFSUX
STFD
STFDU
STFDX
STFDUX
STFIWX
LFDP
LFDPX
STFDP
STFDPX
FMR
FMRCC
FABS
FABSCC
FNABS
FNABSCC
FNEG
FNEGCC
FCPSGN
FCPSGNCC
FMRGEW
FMRGOW
FADD
FADDCC
FADDS
FADDSCC
FSUB
FSUBCC
FSUBS
FSUBSCC
FMUL
FMULCC
FMULS
FMULSCC
FDIV
FDIVCC
FDIVS
FDIVSCC
FSQRT
FSQRTCC
FSQRTS
FSQRTSCC
FRE
FRECC
FRES
FRESCC
FRSQRTE
FRSQRTECC
FRSQRTES
FRSQRTESCC
FTDIV
FTSQRT
FMADD
FMADDCC
FMADDS
FMADDSCC
FMSUB
FMSUBCC
FMSUBS
FMSUBSCC
FNMADD
FNMADDCC
FNMADDS
FNMADDSCC
FNMSUB
FNMSUBCC
FNMSUBS
FNMSUBSCC
FRSP
FRSPCC
FCTID
FCTIDCC
FCTIDZ
FCTIDZCC
FCTIDU
FCTIDUCC
FCTIDUZ
FCTIDUZCC
FCTIW
FCTIWCC
FCTIWZ
FCTIWZCC
FCTIWU
FCTIWUCC
FCTIWUZ
FCTIWUZCC
FCFID
FCFIDCC
FCFIDU
FCFIDUCC
FCFIDS
FCFIDSCC
FCFIDUS
FCFIDUSCC
FRIN
FRINCC
FRIZ
FRIZCC
FRIP
FRIPCC
FRIM
FRIMCC
FCMPU
FCMPO
FSEL
FSELCC
MFFS
MFFSCC
MCRFS
MTFSFI
MTFSFICC
MTFSF
MTFSFCC
MTFSB0
MTFSB0CC
MTFSB1
MTFSB1CC
LVEBX
LVEHX
LVEWX
LVX
LVXL
STVEBX
STVEHX
STVEWX
STVX
STVXL
LVSL
LVSR
VPKPX
VPKSDSS
VPKSDUS
VPKSHSS
VPKSHUS
VPKSWSS
VPKSWUS
VPKUDUM
VPKUDUS
VPKUHUM
VPKUHUS
VPKUWUM
VPKUWUS
VUPKHPX
VUPKLPX
VUPKHSB
VUPKHSH
VUPKHSW
VUPKLSB
VUPKLSH
VUPKLSW
VMRGHB
VMRGHH
VMRGLB
VMRGLH
VMRGHW
VMRGLW
VMRGEW
VMRGOW
VSPLTB
VSPLTH
VSPLTW
VSPLTISB
VSPLTISH
VSPLTISW
VPERM
VSEL
VSL
VSLDOI
VSLO
VSR
VSRO
VADDCUW
VADDSBS
VADDSHS
VADDSWS
VADDUBM
VADDUDM
VADDUHM
VADDUWM
VADDUBS
VADDUHS
VADDUWS
VADDUQM
VADDEUQM
VADDCUQ
VADDECUQ
VSUBCUW
VSUBSBS
VSUBSHS
VSUBSWS
VSUBUBM
VSUBUDM
VSUBUHM
VSUBUWM
VSUBUBS
VSUBUHS
VSUBUWS
VSUBUQM
VSUBEUQM
VSUBCUQ
VSUBECUQ
VMULESB
VMULEUB
VMULOSB
VMULOUB
VMULESH
VMULEUH
VMULOSH
VMULOUH
VMULESW
VMULEUW
VMULOSW
VMULOUW
VMULUWM
VMHADDSHS
VMHRADDSHS
VMLADDUHM
VMSUMUBM
VMSUMMBM
VMSUMSHM
VMSUMSHS
VMSUMUHM
VMSUMUHS
VSUMSWS
VSUM2SWS
VSUM4SBS
VSUM4SHS
VSUM4UBS
VAVGSB
VAVGSH
VAVGSW
VAVGUB
VAVGUW
VAVGUH
VMAXSB
VMAXSD
VMAXUB
VMAXUD
VMAXSH
VMAXSW
VMAXUH
VMAXUW
VMINSB
VMINSD
VMINUB
VMINUD
VMINSH
VMINSW
VMINUH
VMINUW
VCMPEQUB
VCMPEQUBCC
VCMPEQUH
VCMPEQUHCC
VCMPEQUW
VCMPEQUWCC
VCMPEQUD
VCMPEQUDCC
VCMPGTSB
VCMPGTSBCC
VCMPGTSD
VCMPGTSDCC
VCMPGTSH
VCMPGTSHCC
VCMPGTSW
VCMPGTSWCC
VCMPGTUB
VCMPGTUBCC
VCMPGTUD
VCMPGTUDCC
VCMPGTUH
VCMPGTUHCC
VCMPGTUW
VCMPGTUWCC
VAND
VANDC
VEQV
VNAND
VORC
VNOR
VOR
VXOR
VRLB
VRLH
VRLW
VRLD
VSLB
VSLH
VSLW
VSLD
VSRB
VSRH
VSRW
VSRD
VSRAB
VSRAH
VSRAW
VSRAD
VADDFP
VSUBFP
VMADDFP
VNMSUBFP
VMAXFP
VMINFP
VCTSXS
VCTUXS
VCFSX
VCFUX
VRFIM
VRFIN
VRFIP
VRFIZ
VCMPBFP
VCMPBFPCC
VCMPEQFP
VCMPEQFPCC
VCMPGEFP
VCMPGEFPCC
VCMPGTFP
VCMPGTFPCC
VEXPTEFP
VLOGEFP
VREFP
VRSQRTEFP
VCIPHER
VCIPHERLAST
VNCIPHER
VNCIPHERLAST
VSBOX
VSHASIGMAD
VSHASIGMAW
VPMSUMB
VPMSUMD
VPMSUMH
VPMSUMW
VPERMXOR
VGBBD
VCLZB
VCLZH
VCLZW
VCLZD
VPOPCNTB
VPOPCNTD
VPOPCNTH
VPOPCNTW
VBPERMQ
BCDADDCC
BCDSUBCC
MTVSCR
MFVSCR
DADD
DADDCC
DSUB
DSUBCC
DMUL
DMULCC
DDIV
DDIVCC
DCMPU
DCMPO
DTSTDC
DTSTDG
DTSTEX
DTSTSF
DQUAI
DQUAICC
DQUA
DQUACC
DRRND
DRRNDCC
DRINTX
DRINTXCC
DRINTN
DRINTNCC
DCTDP
DCTDPCC
DCTQPQ
DCTQPQCC
DRSP
DRSPCC
DRDPQ
DRDPQCC
DCFFIX
DCFFIXCC
DCFFIXQ
DCFFIXQCC
DCTFIX
DCTFIXCC
DDEDPD
DDEDPDCC
DENBCD
DENBCDCC
DXEX
DXEXCC
DIEX
DIEXCC
DSCLI
DSCLICC
DSCRI
DSCRICC
LXSDX
LXSIWAX
LXSIWZX
LXSSPX
LXVD2X
LXVDSX
LXVW4X
STXSDX
STXSIWX
STXSSPX
STXVD2X
STXVW4X
XSABSDP
XSADDDP
XSADDSP
XSCMPODP
XSCMPUDP
XSCPSGNDP
XSCVDPSP
XSCVDPSPN
XSCVDPSXDS
XSCVDPSXWS
XSCVDPUXDS
XSCVDPUXWS
XSCVSPDP
XSCVSPDPN
XSCVSXDDP
XSCVSXDSP
XSCVUXDDP
XSCVUXDSP
XSDIVDP
XSDIVSP
XSMADDADP
XSMADDASP
XSMAXDP
XSMINDP
XSMSUBADP
XSMSUBASP
XSMULDP
XSMULSP
XSNABSDP
XSNEGDP
XSNMADDADP
XSNMADDASP
XSNMSUBADP
XSNMSUBASP
XSRDPI
XSRDPIC
XSRDPIM
XSRDPIP
XSRDPIZ
XSREDP
XSRESP
XSRSP
XSRSQRTEDP
XSRSQRTESP
XSSQRTDP
XSSQRTSP
XSSUBDP
XSSUBSP
XSTDIVDP
XSTSQRTDP
XVABSDP
XVABSSP
XVADDDP
XVADDSP
XVCMPEQDP
XVCMPEQDPCC
XVCMPEQSP
XVCMPEQSPCC
XVCMPGEDP
XVCMPGEDPCC
XVCMPGESP
XVCMPGESPCC
XVCMPGTDP
XVCMPGTDPCC
XVCMPGTSP
XVCMPGTSPCC
XVCPSGNDP
XVCPSGNSP
XVCVDPSP
XVCVDPSXDS
XVCVDPSXWS
XVCVDPUXDS
XVCVDPUXWS
XVCVSPDP
XVCVSPSXDS
XVCVSPSXWS
XVCVSPUXDS
XVCVSPUXWS
XVCVSXDDP
XVCVSXDSP
XVCVSXWDP
XVCVSXWSP
XVCVUXDDP
XVCVUXDSP
XVCVUXWDP
XVCVUXWSP
XVDIVDP
XVDIVSP
XVMADDADP
XVMADDASP
XVMAXDP
XVMAXSP
XVMINDP
XVMINSP
XVMSUBADP
XVMSUBASP
XVMULDP
XVMULSP
XVNABSDP
XVNABSSP
XVNEGDP
XVNEGSP
XVNMADDADP
XVNMADDASP
XVNMSUBADP
XVNMSUBASP
XVRDPI
XVRDPIC
XVRDPIM
XVRDPIP
XVRDPIZ
XVREDP
XVRESP
XVRSPI
XVRSPIC
XVRSPIM
XVRSPIP
XVRSPIZ
XVRSQRTEDP
XVRSQRTESP
XVSQRTDP
XVSQRTSP
XVSUBDP
XVSUBSP
XVTDIVDP
XVTDIVSP
XVTSQRTDP
XVTSQRTSP
XXLAND
XXLANDC
XXLEQV
XXLNAND
XXLORC
XXLNOR
XXLOR
XXLXOR
XXMRGHW
XXMRGLW
XXPERMDI
XXSEL
XXSLDWI
XXSPLTW
BRINC
EVABS
EVADDIW
EVADDSMIAAW
EVADDSSIAAW
EVADDUMIAAW
EVADDUSIAAW
EVADDW
EVAND
EVCMPEQ
EVANDC
EVCMPGTS
EVCMPGTU
EVCMPLTU
EVCMPLTS
EVCNTLSW
EVCNTLZW
EVDIVWS
EVDIVWU
EVEQV
EVEXTSB
EVEXTSH
EVLDD
EVLDH
EVLDDX
EVLDHX
EVLDW
EVLHHESPLAT
EVLDWX
EVLHHESPLATX
EVLHHOSSPLAT
EVLHHOUSPLAT
EVLHHOSSPLATX
EVLHHOUSPLATX
EVLWHE
EVLWHOS
EVLWHEX
EVLWHOSX
EVLWHOU
EVLWHSPLAT
EVLWHOUX
EVLWHSPLATX
EVLWWSPLAT
EVMERGEHI
EVLWWSPLATX
EVMERGELO
EVMERGEHILO
EVMHEGSMFAA
EVMERGELOHI
EVMHEGSMFAN
EVMHEGSMIAA
EVMHEGUMIAA
EVMHEGSMIAN
EVMHEGUMIAN
EVMHESMF
EVMHESMFAAW
EVMHESMFA
EVMHESMFANW
EVMHESMI
EVMHESMIAAW
EVMHESMIA
EVMHESMIANW
EVMHESSF
EVMHESSFA
EVMHESSFAAW
EVMHESSFANW
EVMHESSIAAW
EVMHESSIANW
EVMHEUMI
EVMHEUMIAAW
EVMHEUMIA
EVMHEUMIANW
EVMHEUSIAAW
EVMHEUSIANW
EVMHOGSMFAA
EVMHOGSMIAA
EVMHOGSMFAN
EVMHOGSMIAN
EVMHOGUMIAA
EVMHOSMF
EVMHOGUMIAN
EVMHOSMFA
EVMHOSMFAAW
EVMHOSMI
EVMHOSMFANW
EVMHOSMIA
EVMHOSMIAAW
EVMHOSMIANW
EVMHOSSF
EVMHOSSFA
EVMHOSSFAAW
EVMHOSSFANW
EVMHOSSIAAW
EVMHOUMI
EVMHOSSIANW
EVMHOUMIA
EVMHOUMIAAW
EVMHOUSIAAW
EVMHOUMIANW
EVMHOUSIANW
EVMRA
EVMWHSMF
EVMWHSMI
EVMWHSMFA
EVMWHSMIA
EVMWHSSF
EVMWHUMI
EVMWHSSFA
EVMWHUMIA
EVMWLSMIAAW
EVMWLSSIAAW
EVMWLSMIANW
EVMWLSSIANW
EVMWLUMI
EVMWLUMIAAW
EVMWLUMIA
EVMWLUMIANW
EVMWLUSIAAW
EVMWSMF
EVMWLUSIANW
EVMWSMFA
EVMWSMFAA
EVMWSMI
EVMWSMIAA
EVMWSMFAN
EVMWSMIA
EVMWSMIAN
EVMWSSF
EVMWSSFA
EVMWSSFAA
EVMWUMI
EVMWSSFAN
EVMWUMIA
EVMWUMIAA
EVNAND
EVMWUMIAN
EVNEG
EVNOR
EVORC
EVOR
EVRLW
EVRLWI
EVSEL
EVRNDW
EVSLW
EVSPLATFI
EVSRWIS
EVSLWI
EVSPLATI
EVSRWIU
EVSRWS
EVSTDD
EVSRWU
EVSTDDX
EVSTDH
EVSTDW
EVSTDHX
EVSTDWX
EVSTWHE
EVSTWHO
EVSTWWE
EVSTWHEX
EVSTWHOX
EVSTWWEX
EVSTWWO
EVSUBFSMIAAW
EVSTWWOX
EVSUBFSSIAAW
EVSUBFUMIAAW
EVSUBFUSIAAW
EVSUBFW
EVSUBIFW
EVXOR
EVFSABS
EVFSNABS
EVFSNEG
EVFSADD
EVFSMUL
EVFSSUB
EVFSDIV
EVFSCMPGT
EVFSCMPLT
EVFSCMPEQ
EVFSTSTGT
EVFSTSTLT
EVFSTSTEQ
EVFSCFSI
EVFSCFSF
EVFSCFUI
EVFSCFUF
EVFSCTSI
EVFSCTUI
EVFSCTSIZ
EVFSCTUIZ
EVFSCTSF
EVFSCTUF
EFSABS
EFSNEG
EFSNABS
EFSADD
EFSMUL
EFSSUB
EFSDIV
EFSCMPGT
EFSCMPLT
EFSCMPEQ
EFSTSTGT
EFSTSTLT
EFSTSTEQ
EFSCFSI
EFSCFSF
EFSCTSI
EFSCFUI
EFSCFUF
EFSCTUI
EFSCTSIZ
EFSCTSF
EFSCTUIZ
EFSCTUF
EFDABS
EFDNEG
EFDNABS
EFDADD
EFDMUL
EFDSUB
EFDDIV
EFDCMPGT
EFDCMPEQ
EFDCMPLT
EFDTSTGT
EFDTSTLT
EFDCFSI
EFDTSTEQ
EFDCFUI
EFDCFSID
EFDCFSF
EFDCFUF
EFDCFUID
EFDCTSI
EFDCTUI
EFDCTSIDZ
EFDCTUIDZ
EFDCTSIZ
EFDCTSF
EFDCTUF
EFDCTUIZ
EFDCFS
EFSCFD
DLMZB
DLMZBCC
MACCHW
MACCHWCC
MACCHWO
MACCHWOCC
MACCHWS
MACCHWSCC
MACCHWSO
MACCHWSOCC
MACCHWU
MACCHWUCC
MACCHWUO
MACCHWUOCC
MACCHWSU
MACCHWSUCC
MACCHWSUO
MACCHWSUOCC
MACHHW
MACHHWCC
MACHHWO
MACHHWOCC
MACHHWS
MACHHWSCC
MACHHWSO
MACHHWSOCC
MACHHWU
MACHHWUCC
MACHHWUO
MACHHWUOCC
MACHHWSU
MACHHWSUCC
MACHHWSUO
MACHHWSUOCC
MACLHW
MACLHWCC
MACLHWO
MACLHWOCC
MACLHWS
MACLHWSCC
MACLHWSO
MACLHWSOCC
MACLHWU
MACLHWUCC
MACLHWUO
MACLHWUOCC
MULCHW
MULCHWCC
MACLHWSU
MACLHWSUCC
MACLHWSUO
MACLHWSUOCC
MULCHWU
MULCHWUCC
MULHHW
MULHHWCC
MULLHW
MULLHWCC
MULHHWU
MULHHWUCC
MULLHWU
MULLHWUCC
NMACCHW
NMACCHWCC
NMACCHWO
NMACCHWOCC
NMACCHWS
NMACCHWSCC
NMACCHWSO
NMACCHWSOCC
NMACHHW
NMACHHWCC
NMACHHWO
NMACHHWOCC
NMACHHWS
NMACHHWSCC
NMACHHWSO
NMACHHWSOCC
NMACLHW
NMACLHWCC
NMACLHWO
NMACLHWOCC
NMACLHWS
NMACLHWSCC
NMACLHWSO
NMACLHWSOCC
ICBI
ICBT
DCBA
DCBT
DCBTST
DCBZ
DCBST
DCBF
ISYNC
LBARX
LHARX
LWARX
STBCXCC
STHCXCC
STWCXCC
LDARX
STDCXCC
LQARX
STQCXCC
SYNC
EIEIO
MBAR
WAIT
TBEGINCC
TENDCC
TABORTCC
TABORTWCCC
TABORTWCICC
TABORTDCCC
TABORTDCICC
TSRCC
TCHECK
MFTB
RFEBB
LBDX
LHDX
LWDX
LDDX
LFDDX
STBDX
STHDX
STWDX
STDDX
STFDDX
DSN
ECIWX
ECOWX
RFID
HRFID
DOZE
NAP
SLEEP
RVWINKLE
LBZCIX
LWZCIX
LHZCIX
LDCIX
STBCIX
STWCIX
STHCIX
STDCIX
TRECLAIMCC
TRECHKPTCC
MTMSR
MTMSRD
MFMSR
SLBIE
SLBIA
SLBMTE
SLBMFEV
SLBMFEE
SLBFEECC
MTSR
MTSRIN
MFSR
MFSRIN
TLBIE
TLBIEL
TLBIA
TLBSYNC
MSGSND
MSGCLR
MSGSNDP
MSGCLRP
MTTMR
RFI
RFCI
RFDI
RFMCI
RFGI
EHPRIV
MTDCR
MTDCRX
MFDCR
MFDCRX
WRTEE
WRTEEI
LBEPX
LHEPX
LWEPX
LDEPX
STBEPX
STHEPX
STWEPX
STDEPX
DCBSTEP
DCBTEP
DCBFEP
DCBTSTEP
ICBIEP
DCBZEP
LFDEPX
STFDEPX
EVLDDEPX
EVSTDDEPX
LVEPX
LVEPXL
STVEPX
STVEPXL
DCBI
DCBLQCC
ICBLQCC
DCBTLS
DCBTSTLS
ICBTLS
ICBLC
DCBLC
TLBIVAX
TLBILX
TLBSX
TLBSRXCC
TLBRE
TLBWE
DNH
DCI
ICI
DCREAD
ICREAD
MFPMR
MTPMR
ADDEX
DARN
MADDHD
MADDHDU
MADDLD
CMPRB
CMPEQB
EXTSWSLI
EXTSWSLICC
MFVSRLD
MTVSRDD
MTVSRWS
MCRXRX
COPY
PASTECC
)
func GNUSyntax(inst Inst) string
GNUSyntax returns the GNU assembler syntax for the instruction, as defined by GNU binutils. This form typically matches the syntax defined in the Power ISA Reference Manual.
type Arg interface {
IsArg()
String() string
}
An Arg is a single instruction argument, one of these types: Reg, CondReg, SpReg, Imm, PCRel, Label, or Offset.
type ArgType int8
const (
TypeUnknown ArgType = iota
TypePCRel // PC-relative address
TypeLabel // absolute address
TypeReg // integer register
TypeCondRegBit // conditional register bit (0-31)
TypeCondRegField // conditional register field (0-7)
TypeFPReg // floating point register
TypeVecReg // vector register
TypeVecSReg // VSX register
TypeSpReg // special register (depends on Op)
TypeImmSigned // signed immediate
TypeImmUnsigned // unsigned immediate/flag/mask, this is the catch-all type
TypeOffset // signed offset in load/store
TypeLast // must be the last one
)
func (t ArgType) GoString() string
func (t ArgType) String() string
type Args [5]Arg
An Args holds the instruction arguments. If an instruction has fewer than 4 arguments, the final elements in the array are nil.
type BitField struct {
Offs uint8 // the offset of the left-most bit.
Bits uint8 // length in bits.
}
A BitField is a bit-field in a 32-bit word. Bits are counted from 0 from the MSB to 31 as the LSB.
func (b BitField) Parse(i uint32) uint32
Parse extracts the bitfield b from i, and return it as an unsigned integer. Parse will panic if b is invalid.
func (b BitField) ParseSigned(i uint32) int32
ParseSigned extracts the bitfield b from i, and return it as a signed integer. ParseSigned will panic if b is invalid.
func (b BitField) String() string
type BitFields []BitField
BitFields is a series of BitFields representing a single number.
func (bs *BitFields) Append(b BitField)
func (bs BitFields) Parse(i uint32) uint32
Parse extracts the bitfields from i, concatenate them and return the result as an unsigned integer. Parse will panic if any bitfield in b is invalid.
func (bs BitFields) ParseSigned(i uint32) int32
Parse extracts the bitfields from i, concatenate them and return the result as a signed integer. Parse will panic if any bitfield in b is invalid.
func (bs BitFields) String() string
type CondReg int8
CondReg is a bit or field in the conditon register.
func (CondReg) IsArg()
func (c CondReg) String() string
type Imm int32
Imm represents an immediate number.
func (Imm) IsArg()
func (i Imm) String() string
type Inst struct {
Op Op // Opcode mnemonic
Enc uint32 // Raw encoding bits
Len int // Length of encoding in bytes.
Args Args // Instruction arguments, in Power ISA manual order.
}
func Decode(src []byte, ord binary.ByteOrder) (inst Inst, err error)
Decode decodes the leading bytes in src as a single instruction using byte order ord.
func (i Inst) String() string
type Label uint32
A Label is a code (text) address, used only in absolute branch instructions.
func (Label) IsArg()
func (l Label) String() string
type Offset int32
Offset represents a memory offset immediate.
func (Offset) IsArg()
func (o Offset) String() string
type Op uint16
An Op is an instruction operation.
func (o Op) String() string
type PCRel int32
PCRel is a PC-relative offset, used only in branch instructions.
func (PCRel) IsArg()
func (r PCRel) String() string
type Reg uint16
A Reg is a single register. The zero value means R0, not the absence of a register. It also includes special registers.
func (Reg) IsArg()
func (r Reg) String() string
type SpReg uint16
SpReg is a special register, its meaning depends on Op.
const (
SpRegZero SpReg = 0
)
func (SpReg) IsArg()
func (s SpReg) String() string