Source file src/pkg/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go
1
2
3
4 package ppc64asm
5
6 const (
7 _ Op = iota
8 CNTLZW
9 CNTLZWCC
10 B
11 BA
12 BL
13 BLA
14 BC
15 BCA
16 BCL
17 BCLA
18 BCLR
19 BCLRL
20 BCCTR
21 BCCTRL
22 BCTAR
23 BCTARL
24 CRAND
25 CROR
26 CRNAND
27 CRXOR
28 CRNOR
29 CRANDC
30 MCRF
31 CREQV
32 CRORC
33 SC
34 CLRBHRB
35 MFBHRBE
36 LBZ
37 LBZU
38 LBZX
39 LBZUX
40 LHZ
41 LHZU
42 LHZX
43 LHZUX
44 LHA
45 LHAU
46 LHAX
47 LHAUX
48 LWZ
49 LWZU
50 LWZX
51 LWZUX
52 LWA
53 LWAX
54 LWAUX
55 LD
56 LDU
57 LDX
58 LDUX
59 STB
60 STBU
61 STBX
62 STBUX
63 STH
64 STHU
65 STHX
66 STHUX
67 STW
68 STWU
69 STWX
70 STWUX
71 STD
72 STDU
73 STDX
74 STDUX
75 LQ
76 STQ
77 LHBRX
78 LWBRX
79 STHBRX
80 STWBRX
81 LDBRX
82 STDBRX
83 LMW
84 STMW
85 LSWI
86 LSWX
87 STSWI
88 STSWX
89 LI
90 ADDI
91 LIS
92 ADDIS
93 ADD
94 ADDCC
95 ADDO
96 ADDOCC
97 ADDIC
98 SUBF
99 SUBFCC
100 SUBFO
101 SUBFOCC
102 ADDICCC
103 SUBFIC
104 ADDC
105 ADDCCC
106 ADDCO
107 ADDCOCC
108 SUBFC
109 SUBFCCC
110 SUBFCO
111 SUBFCOCC
112 ADDE
113 ADDECC
114 ADDEO
115 ADDEOCC
116 ADDME
117 ADDMECC
118 ADDMEO
119 ADDMEOCC
120 SUBFE
121 SUBFECC
122 SUBFEO
123 SUBFEOCC
124 SUBFME
125 SUBFMECC
126 SUBFMEO
127 SUBFMEOCC
128 ADDZE
129 ADDZECC
130 ADDZEO
131 ADDZEOCC
132 SUBFZE
133 SUBFZECC
134 SUBFZEO
135 SUBFZEOCC
136 NEG
137 NEGCC
138 NEGO
139 NEGOCC
140 MULLI
141 MULLW
142 MULLWCC
143 MULLWO
144 MULLWOCC
145 MULHW
146 MULHWCC
147 MULHWU
148 MULHWUCC
149 DIVW
150 DIVWCC
151 DIVWO
152 DIVWOCC
153 DIVWU
154 DIVWUCC
155 DIVWUO
156 DIVWUOCC
157 DIVWE
158 DIVWECC
159 DIVWEO
160 DIVWEOCC
161 DIVWEU
162 DIVWEUCC
163 DIVWEUO
164 DIVWEUOCC
165 MULLD
166 MULLDCC
167 MULLDO
168 MULLDOCC
169 MULHDU
170 MULHDUCC
171 MULHD
172 MULHDCC
173 DIVD
174 DIVDCC
175 DIVDO
176 DIVDOCC
177 DIVDU
178 DIVDUCC
179 DIVDUO
180 DIVDUOCC
181 DIVDE
182 DIVDECC
183 DIVDEO
184 DIVDEOCC
185 DIVDEU
186 DIVDEUCC
187 DIVDEUO
188 DIVDEUOCC
189 CMPWI
190 CMPDI
191 CMPW
192 CMPD
193 CMPLWI
194 CMPLDI
195 CMPLW
196 CMPLD
197 TWI
198 TW
199 TDI
200 ISEL
201 TD
202 ANDICC
203 ANDISCC
204 ORI
205 ORIS
206 XORI
207 XORIS
208 AND
209 ANDCC
210 XOR
211 XORCC
212 NAND
213 NANDCC
214 OR
215 ORCC
216 NOR
217 NORCC
218 ANDC
219 ANDCCC
220 EXTSB
221 EXTSBCC
222 EQV
223 EQVCC
224 ORC
225 ORCCC
226 EXTSH
227 EXTSHCC
228 CMPB
229 POPCNTB
230 POPCNTW
231 PRTYD
232 PRTYW
233 EXTSW
234 EXTSWCC
235 CNTLZD
236 CNTLZDCC
237 POPCNTD
238 BPERMD
239 RLWINM
240 RLWINMCC
241 RLWNM
242 RLWNMCC
243 RLWIMI
244 RLWIMICC
245 RLDICL
246 RLDICLCC
247 RLDICR
248 RLDICRCC
249 RLDIC
250 RLDICCC
251 RLDCL
252 RLDCLCC
253 RLDCR
254 RLDCRCC
255 RLDIMI
256 RLDIMICC
257 SLW
258 SLWCC
259 SRW
260 SRWCC
261 SRAWI
262 SRAWICC
263 SRAW
264 SRAWCC
265 SLD
266 SLDCC
267 SRD
268 SRDCC
269 SRADI
270 SRADICC
271 SRAD
272 SRADCC
273 CDTBCD
274 CBCDTD
275 ADDG6S
276 MTSPR
277 MFSPR
278 MTCRF
279 MFCR
280 MTSLE
281 MFVSRD
282 MFVSRWZ
283 MTVSRD
284 MTVSRWA
285 MTVSRWZ
286 MTOCRF
287 MFOCRF
288 MCRXR
289 MTDCRUX
290 MFDCRUX
291 LFS
292 LFSU
293 LFSX
294 LFSUX
295 LFD
296 LFDU
297 LFDX
298 LFDUX
299 LFIWAX
300 LFIWZX
301 STFS
302 STFSU
303 STFSX
304 STFSUX
305 STFD
306 STFDU
307 STFDX
308 STFDUX
309 STFIWX
310 LFDP
311 LFDPX
312 STFDP
313 STFDPX
314 FMR
315 FMRCC
316 FABS
317 FABSCC
318 FNABS
319 FNABSCC
320 FNEG
321 FNEGCC
322 FCPSGN
323 FCPSGNCC
324 FMRGEW
325 FMRGOW
326 FADD
327 FADDCC
328 FADDS
329 FADDSCC
330 FSUB
331 FSUBCC
332 FSUBS
333 FSUBSCC
334 FMUL
335 FMULCC
336 FMULS
337 FMULSCC
338 FDIV
339 FDIVCC
340 FDIVS
341 FDIVSCC
342 FSQRT
343 FSQRTCC
344 FSQRTS
345 FSQRTSCC
346 FRE
347 FRECC
348 FRES
349 FRESCC
350 FRSQRTE
351 FRSQRTECC
352 FRSQRTES
353 FRSQRTESCC
354 FTDIV
355 FTSQRT
356 FMADD
357 FMADDCC
358 FMADDS
359 FMADDSCC
360 FMSUB
361 FMSUBCC
362 FMSUBS
363 FMSUBSCC
364 FNMADD
365 FNMADDCC
366 FNMADDS
367 FNMADDSCC
368 FNMSUB
369 FNMSUBCC
370 FNMSUBS
371 FNMSUBSCC
372 FRSP
373 FRSPCC
374 FCTID
375 FCTIDCC
376 FCTIDZ
377 FCTIDZCC
378 FCTIDU
379 FCTIDUCC
380 FCTIDUZ
381 FCTIDUZCC
382 FCTIW
383 FCTIWCC
384 FCTIWZ
385 FCTIWZCC
386 FCTIWU
387 FCTIWUCC
388 FCTIWUZ
389 FCTIWUZCC
390 FCFID
391 FCFIDCC
392 FCFIDU
393 FCFIDUCC
394 FCFIDS
395 FCFIDSCC
396 FCFIDUS
397 FCFIDUSCC
398 FRIN
399 FRINCC
400 FRIZ
401 FRIZCC
402 FRIP
403 FRIPCC
404 FRIM
405 FRIMCC
406 FCMPU
407 FCMPO
408 FSEL
409 FSELCC
410 MFFS
411 MFFSCC
412 MCRFS
413 MTFSFI
414 MTFSFICC
415 MTFSF
416 MTFSFCC
417 MTFSB0
418 MTFSB0CC
419 MTFSB1
420 MTFSB1CC
421 LVEBX
422 LVEHX
423 LVEWX
424 LVX
425 LVXL
426 STVEBX
427 STVEHX
428 STVEWX
429 STVX
430 STVXL
431 LVSL
432 LVSR
433 VPKPX
434 VPKSDSS
435 VPKSDUS
436 VPKSHSS
437 VPKSHUS
438 VPKSWSS
439 VPKSWUS
440 VPKUDUM
441 VPKUDUS
442 VPKUHUM
443 VPKUHUS
444 VPKUWUM
445 VPKUWUS
446 VUPKHPX
447 VUPKLPX
448 VUPKHSB
449 VUPKHSH
450 VUPKHSW
451 VUPKLSB
452 VUPKLSH
453 VUPKLSW
454 VMRGHB
455 VMRGHH
456 VMRGLB
457 VMRGLH
458 VMRGHW
459 VMRGLW
460 VMRGEW
461 VMRGOW
462 VSPLTB
463 VSPLTH
464 VSPLTW
465 VSPLTISB
466 VSPLTISH
467 VSPLTISW
468 VPERM
469 VSEL
470 VSL
471 VSLDOI
472 VSLO
473 VSR
474 VSRO
475 VADDCUW
476 VADDSBS
477 VADDSHS
478 VADDSWS
479 VADDUBM
480 VADDUDM
481 VADDUHM
482 VADDUWM
483 VADDUBS
484 VADDUHS
485 VADDUWS
486 VADDUQM
487 VADDEUQM
488 VADDCUQ
489 VADDECUQ
490 VSUBCUW
491 VSUBSBS
492 VSUBSHS
493 VSUBSWS
494 VSUBUBM
495 VSUBUDM
496 VSUBUHM
497 VSUBUWM
498 VSUBUBS
499 VSUBUHS
500 VSUBUWS
501 VSUBUQM
502 VSUBEUQM
503 VSUBCUQ
504 VSUBECUQ
505 VMULESB
506 VMULEUB
507 VMULOSB
508 VMULOUB
509 VMULESH
510 VMULEUH
511 VMULOSH
512 VMULOUH
513 VMULESW
514 VMULEUW
515 VMULOSW
516 VMULOUW
517 VMULUWM
518 VMHADDSHS
519 VMHRADDSHS
520 VMLADDUHM
521 VMSUMUBM
522 VMSUMMBM
523 VMSUMSHM
524 VMSUMSHS
525 VMSUMUHM
526 VMSUMUHS
527 VSUMSWS
528 VSUM2SWS
529 VSUM4SBS
530 VSUM4SHS
531 VSUM4UBS
532 VAVGSB
533 VAVGSH
534 VAVGSW
535 VAVGUB
536 VAVGUW
537 VAVGUH
538 VMAXSB
539 VMAXSD
540 VMAXUB
541 VMAXUD
542 VMAXSH
543 VMAXSW
544 VMAXUH
545 VMAXUW
546 VMINSB
547 VMINSD
548 VMINUB
549 VMINUD
550 VMINSH
551 VMINSW
552 VMINUH
553 VMINUW
554 VCMPEQUB
555 VCMPEQUBCC
556 VCMPEQUH
557 VCMPEQUHCC
558 VCMPEQUW
559 VCMPEQUWCC
560 VCMPEQUD
561 VCMPEQUDCC
562 VCMPGTSB
563 VCMPGTSBCC
564 VCMPGTSD
565 VCMPGTSDCC
566 VCMPGTSH
567 VCMPGTSHCC
568 VCMPGTSW
569 VCMPGTSWCC
570 VCMPGTUB
571 VCMPGTUBCC
572 VCMPGTUD
573 VCMPGTUDCC
574 VCMPGTUH
575 VCMPGTUHCC
576 VCMPGTUW
577 VCMPGTUWCC
578 VAND
579 VANDC
580 VEQV
581 VNAND
582 VORC
583 VNOR
584 VOR
585 VXOR
586 VRLB
587 VRLH
588 VRLW
589 VRLD
590 VSLB
591 VSLH
592 VSLW
593 VSLD
594 VSRB
595 VSRH
596 VSRW
597 VSRD
598 VSRAB
599 VSRAH
600 VSRAW
601 VSRAD
602 VADDFP
603 VSUBFP
604 VMADDFP
605 VNMSUBFP
606 VMAXFP
607 VMINFP
608 VCTSXS
609 VCTUXS
610 VCFSX
611 VCFUX
612 VRFIM
613 VRFIN
614 VRFIP
615 VRFIZ
616 VCMPBFP
617 VCMPBFPCC
618 VCMPEQFP
619 VCMPEQFPCC
620 VCMPGEFP
621 VCMPGEFPCC
622 VCMPGTFP
623 VCMPGTFPCC
624 VEXPTEFP
625 VLOGEFP
626 VREFP
627 VRSQRTEFP
628 VCIPHER
629 VCIPHERLAST
630 VNCIPHER
631 VNCIPHERLAST
632 VSBOX
633 VSHASIGMAD
634 VSHASIGMAW
635 VPMSUMB
636 VPMSUMD
637 VPMSUMH
638 VPMSUMW
639 VPERMXOR
640 VGBBD
641 VCLZB
642 VCLZH
643 VCLZW
644 VCLZD
645 VPOPCNTB
646 VPOPCNTD
647 VPOPCNTH
648 VPOPCNTW
649 VBPERMQ
650 BCDADDCC
651 BCDSUBCC
652 MTVSCR
653 MFVSCR
654 DADD
655 DADDCC
656 DSUB
657 DSUBCC
658 DMUL
659 DMULCC
660 DDIV
661 DDIVCC
662 DCMPU
663 DCMPO
664 DTSTDC
665 DTSTDG
666 DTSTEX
667 DTSTSF
668 DQUAI
669 DQUAICC
670 DQUA
671 DQUACC
672 DRRND
673 DRRNDCC
674 DRINTX
675 DRINTXCC
676 DRINTN
677 DRINTNCC
678 DCTDP
679 DCTDPCC
680 DCTQPQ
681 DCTQPQCC
682 DRSP
683 DRSPCC
684 DRDPQ
685 DRDPQCC
686 DCFFIX
687 DCFFIXCC
688 DCFFIXQ
689 DCFFIXQCC
690 DCTFIX
691 DCTFIXCC
692 DDEDPD
693 DDEDPDCC
694 DENBCD
695 DENBCDCC
696 DXEX
697 DXEXCC
698 DIEX
699 DIEXCC
700 DSCLI
701 DSCLICC
702 DSCRI
703 DSCRICC
704 LXSDX
705 LXSIWAX
706 LXSIWZX
707 LXSSPX
708 LXVD2X
709 LXVDSX
710 LXVW4X
711 STXSDX
712 STXSIWX
713 STXSSPX
714 STXVD2X
715 STXVW4X
716 XSABSDP
717 XSADDDP
718 XSADDSP
719 XSCMPODP
720 XSCMPUDP
721 XSCPSGNDP
722 XSCVDPSP
723 XSCVDPSPN
724 XSCVDPSXDS
725 XSCVDPSXWS
726 XSCVDPUXDS
727 XSCVDPUXWS
728 XSCVSPDP
729 XSCVSPDPN
730 XSCVSXDDP
731 XSCVSXDSP
732 XSCVUXDDP
733 XSCVUXDSP
734 XSDIVDP
735 XSDIVSP
736 XSMADDADP
737 XSMADDASP
738 XSMAXDP
739 XSMINDP
740 XSMSUBADP
741 XSMSUBASP
742 XSMULDP
743 XSMULSP
744 XSNABSDP
745 XSNEGDP
746 XSNMADDADP
747 XSNMADDASP
748 XSNMSUBADP
749 XSNMSUBASP
750 XSRDPI
751 XSRDPIC
752 XSRDPIM
753 XSRDPIP
754 XSRDPIZ
755 XSREDP
756 XSRESP
757 XSRSP
758 XSRSQRTEDP
759 XSRSQRTESP
760 XSSQRTDP
761 XSSQRTSP
762 XSSUBDP
763 XSSUBSP
764 XSTDIVDP
765 XSTSQRTDP
766 XVABSDP
767 XVABSSP
768 XVADDDP
769 XVADDSP
770 XVCMPEQDP
771 XVCMPEQDPCC
772 XVCMPEQSP
773 XVCMPEQSPCC
774 XVCMPGEDP
775 XVCMPGEDPCC
776 XVCMPGESP
777 XVCMPGESPCC
778 XVCMPGTDP
779 XVCMPGTDPCC
780 XVCMPGTSP
781 XVCMPGTSPCC
782 XVCPSGNDP
783 XVCPSGNSP
784 XVCVDPSP
785 XVCVDPSXDS
786 XVCVDPSXWS
787 XVCVDPUXDS
788 XVCVDPUXWS
789 XVCVSPDP
790 XVCVSPSXDS
791 XVCVSPSXWS
792 XVCVSPUXDS
793 XVCVSPUXWS
794 XVCVSXDDP
795 XVCVSXDSP
796 XVCVSXWDP
797 XVCVSXWSP
798 XVCVUXDDP
799 XVCVUXDSP
800 XVCVUXWDP
801 XVCVUXWSP
802 XVDIVDP
803 XVDIVSP
804 XVMADDADP
805 XVMADDASP
806 XVMAXDP
807 XVMAXSP
808 XVMINDP
809 XVMINSP
810 XVMSUBADP
811 XVMSUBASP
812 XVMULDP
813 XVMULSP
814 XVNABSDP
815 XVNABSSP
816 XVNEGDP
817 XVNEGSP
818 XVNMADDADP
819 XVNMADDASP
820 XVNMSUBADP
821 XVNMSUBASP
822 XVRDPI
823 XVRDPIC
824 XVRDPIM
825 XVRDPIP
826 XVRDPIZ
827 XVREDP
828 XVRESP
829 XVRSPI
830 XVRSPIC
831 XVRSPIM
832 XVRSPIP
833 XVRSPIZ
834 XVRSQRTEDP
835 XVRSQRTESP
836 XVSQRTDP
837 XVSQRTSP
838 XVSUBDP
839 XVSUBSP
840 XVTDIVDP
841 XVTDIVSP
842 XVTSQRTDP
843 XVTSQRTSP
844 XXLAND
845 XXLANDC
846 XXLEQV
847 XXLNAND
848 XXLORC
849 XXLNOR
850 XXLOR
851 XXLXOR
852 XXMRGHW
853 XXMRGLW
854 XXPERMDI
855 XXSEL
856 XXSLDWI
857 XXSPLTW
858 BRINC
859 EVABS
860 EVADDIW
861 EVADDSMIAAW
862 EVADDSSIAAW
863 EVADDUMIAAW
864 EVADDUSIAAW
865 EVADDW
866 EVAND
867 EVCMPEQ
868 EVANDC
869 EVCMPGTS
870 EVCMPGTU
871 EVCMPLTU
872 EVCMPLTS
873 EVCNTLSW
874 EVCNTLZW
875 EVDIVWS
876 EVDIVWU
877 EVEQV
878 EVEXTSB
879 EVEXTSH
880 EVLDD
881 EVLDH
882 EVLDDX
883 EVLDHX
884 EVLDW
885 EVLHHESPLAT
886 EVLDWX
887 EVLHHESPLATX
888 EVLHHOSSPLAT
889 EVLHHOUSPLAT
890 EVLHHOSSPLATX
891 EVLHHOUSPLATX
892 EVLWHE
893 EVLWHOS
894 EVLWHEX
895 EVLWHOSX
896 EVLWHOU
897 EVLWHSPLAT
898 EVLWHOUX
899 EVLWHSPLATX
900 EVLWWSPLAT
901 EVMERGEHI
902 EVLWWSPLATX
903 EVMERGELO
904 EVMERGEHILO
905 EVMHEGSMFAA
906 EVMERGELOHI
907 EVMHEGSMFAN
908 EVMHEGSMIAA
909 EVMHEGUMIAA
910 EVMHEGSMIAN
911 EVMHEGUMIAN
912 EVMHESMF
913 EVMHESMFAAW
914 EVMHESMFA
915 EVMHESMFANW
916 EVMHESMI
917 EVMHESMIAAW
918 EVMHESMIA
919 EVMHESMIANW
920 EVMHESSF
921 EVMHESSFA
922 EVMHESSFAAW
923 EVMHESSFANW
924 EVMHESSIAAW
925 EVMHESSIANW
926 EVMHEUMI
927 EVMHEUMIAAW
928 EVMHEUMIA
929 EVMHEUMIANW
930 EVMHEUSIAAW
931 EVMHEUSIANW
932 EVMHOGSMFAA
933 EVMHOGSMIAA
934 EVMHOGSMFAN
935 EVMHOGSMIAN
936 EVMHOGUMIAA
937 EVMHOSMF
938 EVMHOGUMIAN
939 EVMHOSMFA
940 EVMHOSMFAAW
941 EVMHOSMI
942 EVMHOSMFANW
943 EVMHOSMIA
944 EVMHOSMIAAW
945 EVMHOSMIANW
946 EVMHOSSF
947 EVMHOSSFA
948 EVMHOSSFAAW
949 EVMHOSSFANW
950 EVMHOSSIAAW
951 EVMHOUMI
952 EVMHOSSIANW
953 EVMHOUMIA
954 EVMHOUMIAAW
955 EVMHOUSIAAW
956 EVMHOUMIANW
957 EVMHOUSIANW
958 EVMRA
959 EVMWHSMF
960 EVMWHSMI
961 EVMWHSMFA
962 EVMWHSMIA
963 EVMWHSSF
964 EVMWHUMI
965 EVMWHSSFA
966 EVMWHUMIA
967 EVMWLSMIAAW
968 EVMWLSSIAAW
969 EVMWLSMIANW
970 EVMWLSSIANW
971 EVMWLUMI
972 EVMWLUMIAAW
973 EVMWLUMIA
974 EVMWLUMIANW
975 EVMWLUSIAAW
976 EVMWSMF
977 EVMWLUSIANW
978 EVMWSMFA
979 EVMWSMFAA
980 EVMWSMI
981 EVMWSMIAA
982 EVMWSMFAN
983 EVMWSMIA
984 EVMWSMIAN
985 EVMWSSF
986 EVMWSSFA
987 EVMWSSFAA
988 EVMWUMI
989 EVMWSSFAN
990 EVMWUMIA
991 EVMWUMIAA
992 EVNAND
993 EVMWUMIAN
994 EVNEG
995 EVNOR
996 EVORC
997 EVOR
998 EVRLW
999 EVRLWI
1000 EVSEL
1001 EVRNDW
1002 EVSLW
1003 EVSPLATFI
1004 EVSRWIS
1005 EVSLWI
1006 EVSPLATI
1007 EVSRWIU
1008 EVSRWS
1009 EVSTDD
1010 EVSRWU
1011 EVSTDDX
1012 EVSTDH
1013 EVSTDW
1014 EVSTDHX
1015 EVSTDWX
1016 EVSTWHE
1017 EVSTWHO
1018 EVSTWWE
1019 EVSTWHEX
1020 EVSTWHOX
1021 EVSTWWEX
1022 EVSTWWO
1023 EVSUBFSMIAAW
1024 EVSTWWOX
1025 EVSUBFSSIAAW
1026 EVSUBFUMIAAW
1027 EVSUBFUSIAAW
1028 EVSUBFW
1029 EVSUBIFW
1030 EVXOR
1031 EVFSABS
1032 EVFSNABS
1033 EVFSNEG
1034 EVFSADD
1035 EVFSMUL
1036 EVFSSUB
1037 EVFSDIV
1038 EVFSCMPGT
1039 EVFSCMPLT
1040 EVFSCMPEQ
1041 EVFSTSTGT
1042 EVFSTSTLT
1043 EVFSTSTEQ
1044 EVFSCFSI
1045 EVFSCFSF
1046 EVFSCFUI
1047 EVFSCFUF
1048 EVFSCTSI
1049 EVFSCTUI
1050 EVFSCTSIZ
1051 EVFSCTUIZ
1052 EVFSCTSF
1053 EVFSCTUF
1054 EFSABS
1055 EFSNEG
1056 EFSNABS
1057 EFSADD
1058 EFSMUL
1059 EFSSUB
1060 EFSDIV
1061 EFSCMPGT
1062 EFSCMPLT
1063 EFSCMPEQ
1064 EFSTSTGT
1065 EFSTSTLT
1066 EFSTSTEQ
1067 EFSCFSI
1068 EFSCFSF
1069 EFSCTSI
1070 EFSCFUI
1071 EFSCFUF
1072 EFSCTUI
1073 EFSCTSIZ
1074 EFSCTSF
1075 EFSCTUIZ
1076 EFSCTUF
1077 EFDABS
1078 EFDNEG
1079 EFDNABS
1080 EFDADD
1081 EFDMUL
1082 EFDSUB
1083 EFDDIV
1084 EFDCMPGT
1085 EFDCMPEQ
1086 EFDCMPLT
1087 EFDTSTGT
1088 EFDTSTLT
1089 EFDCFSI
1090 EFDTSTEQ
1091 EFDCFUI
1092 EFDCFSID
1093 EFDCFSF
1094 EFDCFUF
1095 EFDCFUID
1096 EFDCTSI
1097 EFDCTUI
1098 EFDCTSIDZ
1099 EFDCTUIDZ
1100 EFDCTSIZ
1101 EFDCTSF
1102 EFDCTUF
1103 EFDCTUIZ
1104 EFDCFS
1105 EFSCFD
1106 DLMZB
1107 DLMZBCC
1108 MACCHW
1109 MACCHWCC
1110 MACCHWO
1111 MACCHWOCC
1112 MACCHWS
1113 MACCHWSCC
1114 MACCHWSO
1115 MACCHWSOCC
1116 MACCHWU
1117 MACCHWUCC
1118 MACCHWUO
1119 MACCHWUOCC
1120 MACCHWSU
1121 MACCHWSUCC
1122 MACCHWSUO
1123 MACCHWSUOCC
1124 MACHHW
1125 MACHHWCC
1126 MACHHWO
1127 MACHHWOCC
1128 MACHHWS
1129 MACHHWSCC
1130 MACHHWSO
1131 MACHHWSOCC
1132 MACHHWU
1133 MACHHWUCC
1134 MACHHWUO
1135 MACHHWUOCC
1136 MACHHWSU
1137 MACHHWSUCC
1138 MACHHWSUO
1139 MACHHWSUOCC
1140 MACLHW
1141 MACLHWCC
1142 MACLHWO
1143 MACLHWOCC
1144 MACLHWS
1145 MACLHWSCC
1146 MACLHWSO
1147 MACLHWSOCC
1148 MACLHWU
1149 MACLHWUCC
1150 MACLHWUO
1151 MACLHWUOCC
1152 MULCHW
1153 MULCHWCC
1154 MACLHWSU
1155 MACLHWSUCC
1156 MACLHWSUO
1157 MACLHWSUOCC
1158 MULCHWU
1159 MULCHWUCC
1160 MULHHW
1161 MULHHWCC
1162 MULLHW
1163 MULLHWCC
1164 MULHHWU
1165 MULHHWUCC
1166 MULLHWU
1167 MULLHWUCC
1168 NMACCHW
1169 NMACCHWCC
1170 NMACCHWO
1171 NMACCHWOCC
1172 NMACCHWS
1173 NMACCHWSCC
1174 NMACCHWSO
1175 NMACCHWSOCC
1176 NMACHHW
1177 NMACHHWCC
1178 NMACHHWO
1179 NMACHHWOCC
1180 NMACHHWS
1181 NMACHHWSCC
1182 NMACHHWSO
1183 NMACHHWSOCC
1184 NMACLHW
1185 NMACLHWCC
1186 NMACLHWO
1187 NMACLHWOCC
1188 NMACLHWS
1189 NMACLHWSCC
1190 NMACLHWSO
1191 NMACLHWSOCC
1192 ICBI
1193 ICBT
1194 DCBA
1195 DCBT
1196 DCBTST
1197 DCBZ
1198 DCBST
1199 DCBF
1200 ISYNC
1201 LBARX
1202 LHARX
1203 LWARX
1204 STBCXCC
1205 STHCXCC
1206 STWCXCC
1207 LDARX
1208 STDCXCC
1209 LQARX
1210 STQCXCC
1211 SYNC
1212 EIEIO
1213 MBAR
1214 WAIT
1215 TBEGINCC
1216 TENDCC
1217 TABORTCC
1218 TABORTWCCC
1219 TABORTWCICC
1220 TABORTDCCC
1221 TABORTDCICC
1222 TSRCC
1223 TCHECK
1224 MFTB
1225 RFEBB
1226 LBDX
1227 LHDX
1228 LWDX
1229 LDDX
1230 LFDDX
1231 STBDX
1232 STHDX
1233 STWDX
1234 STDDX
1235 STFDDX
1236 DSN
1237 ECIWX
1238 ECOWX
1239 RFID
1240 HRFID
1241 DOZE
1242 NAP
1243 SLEEP
1244 RVWINKLE
1245 LBZCIX
1246 LWZCIX
1247 LHZCIX
1248 LDCIX
1249 STBCIX
1250 STWCIX
1251 STHCIX
1252 STDCIX
1253 TRECLAIMCC
1254 TRECHKPTCC
1255 MTMSR
1256 MTMSRD
1257 MFMSR
1258 SLBIE
1259 SLBIA
1260 SLBMTE
1261 SLBMFEV
1262 SLBMFEE
1263 SLBFEECC
1264 MTSR
1265 MTSRIN
1266 MFSR
1267 MFSRIN
1268 TLBIE
1269 TLBIEL
1270 TLBIA
1271 TLBSYNC
1272 MSGSND
1273 MSGCLR
1274 MSGSNDP
1275 MSGCLRP
1276 MTTMR
1277 RFI
1278 RFCI
1279 RFDI
1280 RFMCI
1281 RFGI
1282 EHPRIV
1283 MTDCR
1284 MTDCRX
1285 MFDCR
1286 MFDCRX
1287 WRTEE
1288 WRTEEI
1289 LBEPX
1290 LHEPX
1291 LWEPX
1292 LDEPX
1293 STBEPX
1294 STHEPX
1295 STWEPX
1296 STDEPX
1297 DCBSTEP
1298 DCBTEP
1299 DCBFEP
1300 DCBTSTEP
1301 ICBIEP
1302 DCBZEP
1303 LFDEPX
1304 STFDEPX
1305 EVLDDEPX
1306 EVSTDDEPX
1307 LVEPX
1308 LVEPXL
1309 STVEPX
1310 STVEPXL
1311 DCBI
1312 DCBLQCC
1313 ICBLQCC
1314 DCBTLS
1315 DCBTSTLS
1316 ICBTLS
1317 ICBLC
1318 DCBLC
1319 TLBIVAX
1320 TLBILX
1321 TLBSX
1322 TLBSRXCC
1323 TLBRE
1324 TLBWE
1325 DNH
1326 DCI
1327 ICI
1328 DCREAD
1329 ICREAD
1330 MFPMR
1331 MTPMR
1332 ADDEX
1333 DARN
1334 MADDHD
1335 MADDHDU
1336 MADDLD
1337 CMPRB
1338 CMPEQB
1339 EXTSWSLI
1340 EXTSWSLICC
1341 MFVSRLD
1342 MTVSRDD
1343 MTVSRWS
1344 MCRXRX
1345 COPY
1346 PASTECC
1347 )
1348
1349 var opstr = [...]string{
1350 CNTLZW: "cntlzw",
1351 CNTLZWCC: "cntlzw.",
1352 B: "b",
1353 BA: "ba",
1354 BL: "bl",
1355 BLA: "bla",
1356 BC: "bc",
1357 BCA: "bca",
1358 BCL: "bcl",
1359 BCLA: "bcla",
1360 BCLR: "bclr",
1361 BCLRL: "bclrl",
1362 BCCTR: "bcctr",
1363 BCCTRL: "bcctrl",
1364 BCTAR: "bctar",
1365 BCTARL: "bctarl",
1366 CRAND: "crand",
1367 CROR: "cror",
1368 CRNAND: "crnand",
1369 CRXOR: "crxor",
1370 CRNOR: "crnor",
1371 CRANDC: "crandc",
1372 MCRF: "mcrf",
1373 CREQV: "creqv",
1374 CRORC: "crorc",
1375 SC: "sc",
1376 CLRBHRB: "clrbhrb",
1377 MFBHRBE: "mfbhrbe",
1378 LBZ: "lbz",
1379 LBZU: "lbzu",
1380 LBZX: "lbzx",
1381 LBZUX: "lbzux",
1382 LHZ: "lhz",
1383 LHZU: "lhzu",
1384 LHZX: "lhzx",
1385 LHZUX: "lhzux",
1386 LHA: "lha",
1387 LHAU: "lhau",
1388 LHAX: "lhax",
1389 LHAUX: "lhaux",
1390 LWZ: "lwz",
1391 LWZU: "lwzu",
1392 LWZX: "lwzx",
1393 LWZUX: "lwzux",
1394 LWA: "lwa",
1395 LWAX: "lwax",
1396 LWAUX: "lwaux",
1397 LD: "ld",
1398 LDU: "ldu",
1399 LDX: "ldx",
1400 LDUX: "ldux",
1401 STB: "stb",
1402 STBU: "stbu",
1403 STBX: "stbx",
1404 STBUX: "stbux",
1405 STH: "sth",
1406 STHU: "sthu",
1407 STHX: "sthx",
1408 STHUX: "sthux",
1409 STW: "stw",
1410 STWU: "stwu",
1411 STWX: "stwx",
1412 STWUX: "stwux",
1413 STD: "std",
1414 STDU: "stdu",
1415 STDX: "stdx",
1416 STDUX: "stdux",
1417 LQ: "lq",
1418 STQ: "stq",
1419 LHBRX: "lhbrx",
1420 LWBRX: "lwbrx",
1421 STHBRX: "sthbrx",
1422 STWBRX: "stwbrx",
1423 LDBRX: "ldbrx",
1424 STDBRX: "stdbrx",
1425 LMW: "lmw",
1426 STMW: "stmw",
1427 LSWI: "lswi",
1428 LSWX: "lswx",
1429 STSWI: "stswi",
1430 STSWX: "stswx",
1431 LI: "li",
1432 ADDI: "addi",
1433 LIS: "lis",
1434 ADDIS: "addis",
1435 ADD: "add",
1436 ADDCC: "add.",
1437 ADDO: "addo",
1438 ADDOCC: "addo.",
1439 ADDIC: "addic",
1440 SUBF: "subf",
1441 SUBFCC: "subf.",
1442 SUBFO: "subfo",
1443 SUBFOCC: "subfo.",
1444 ADDICCC: "addic.",
1445 SUBFIC: "subfic",
1446 ADDC: "addc",
1447 ADDCCC: "addc.",
1448 ADDCO: "addco",
1449 ADDCOCC: "addco.",
1450 SUBFC: "subfc",
1451 SUBFCCC: "subfc.",
1452 SUBFCO: "subfco",
1453 SUBFCOCC: "subfco.",
1454 ADDE: "adde",
1455 ADDECC: "adde.",
1456 ADDEO: "addeo",
1457 ADDEOCC: "addeo.",
1458 ADDME: "addme",
1459 ADDMECC: "addme.",
1460 ADDMEO: "addmeo",
1461 ADDMEOCC: "addmeo.",
1462 SUBFE: "subfe",
1463 SUBFECC: "subfe.",
1464 SUBFEO: "subfeo",
1465 SUBFEOCC: "subfeo.",
1466 SUBFME: "subfme",
1467 SUBFMECC: "subfme.",
1468 SUBFMEO: "subfmeo",
1469 SUBFMEOCC: "subfmeo.",
1470 ADDZE: "addze",
1471 ADDZECC: "addze.",
1472 ADDZEO: "addzeo",
1473 ADDZEOCC: "addzeo.",
1474 SUBFZE: "subfze",
1475 SUBFZECC: "subfze.",
1476 SUBFZEO: "subfzeo",
1477 SUBFZEOCC: "subfzeo.",
1478 NEG: "neg",
1479 NEGCC: "neg.",
1480 NEGO: "nego",
1481 NEGOCC: "nego.",
1482 MULLI: "mulli",
1483 MULLW: "mullw",
1484 MULLWCC: "mullw.",
1485 MULLWO: "mullwo",
1486 MULLWOCC: "mullwo.",
1487 MULHW: "mulhw",
1488 MULHWCC: "mulhw.",
1489 MULHWU: "mulhwu",
1490 MULHWUCC: "mulhwu.",
1491 DIVW: "divw",
1492 DIVWCC: "divw.",
1493 DIVWO: "divwo",
1494 DIVWOCC: "divwo.",
1495 DIVWU: "divwu",
1496 DIVWUCC: "divwu.",
1497 DIVWUO: "divwuo",
1498 DIVWUOCC: "divwuo.",
1499 DIVWE: "divwe",
1500 DIVWECC: "divwe.",
1501 DIVWEO: "divweo",
1502 DIVWEOCC: "divweo.",
1503 DIVWEU: "divweu",
1504 DIVWEUCC: "divweu.",
1505 DIVWEUO: "divweuo",
1506 DIVWEUOCC: "divweuo.",
1507 MULLD: "mulld",
1508 MULLDCC: "mulld.",
1509 MULLDO: "mulldo",
1510 MULLDOCC: "mulldo.",
1511 MULHDU: "mulhdu",
1512 MULHDUCC: "mulhdu.",
1513 MULHD: "mulhd",
1514 MULHDCC: "mulhd.",
1515 DIVD: "divd",
1516 DIVDCC: "divd.",
1517 DIVDO: "divdo",
1518 DIVDOCC: "divdo.",
1519 DIVDU: "divdu",
1520 DIVDUCC: "divdu.",
1521 DIVDUO: "divduo",
1522 DIVDUOCC: "divduo.",
1523 DIVDE: "divde",
1524 DIVDECC: "divde.",
1525 DIVDEO: "divdeo",
1526 DIVDEOCC: "divdeo.",
1527 DIVDEU: "divdeu",
1528 DIVDEUCC: "divdeu.",
1529 DIVDEUO: "divdeuo",
1530 DIVDEUOCC: "divdeuo.",
1531 CMPWI: "cmpwi",
1532 CMPDI: "cmpdi",
1533 CMPW: "cmpw",
1534 CMPD: "cmpd",
1535 CMPLWI: "cmplwi",
1536 CMPLDI: "cmpldi",
1537 CMPLW: "cmplw",
1538 CMPLD: "cmpld",
1539 TWI: "twi",
1540 TW: "tw",
1541 TDI: "tdi",
1542 ISEL: "isel",
1543 TD: "td",
1544 ANDICC: "andi.",
1545 ANDISCC: "andis.",
1546 ORI: "ori",
1547 ORIS: "oris",
1548 XORI: "xori",
1549 XORIS: "xoris",
1550 AND: "and",
1551 ANDCC: "and.",
1552 XOR: "xor",
1553 XORCC: "xor.",
1554 NAND: "nand",
1555 NANDCC: "nand.",
1556 OR: "or",
1557 ORCC: "or.",
1558 NOR: "nor",
1559 NORCC: "nor.",
1560 ANDC: "andc",
1561 ANDCCC: "andc.",
1562 EXTSB: "extsb",
1563 EXTSBCC: "extsb.",
1564 EQV: "eqv",
1565 EQVCC: "eqv.",
1566 ORC: "orc",
1567 ORCCC: "orc.",
1568 EXTSH: "extsh",
1569 EXTSHCC: "extsh.",
1570 CMPB: "cmpb",
1571 POPCNTB: "popcntb",
1572 POPCNTW: "popcntw",
1573 PRTYD: "prtyd",
1574 PRTYW: "prtyw",
1575 EXTSW: "extsw",
1576 EXTSWCC: "extsw.",
1577 CNTLZD: "cntlzd",
1578 CNTLZDCC: "cntlzd.",
1579 POPCNTD: "popcntd",
1580 BPERMD: "bpermd",
1581 RLWINM: "rlwinm",
1582 RLWINMCC: "rlwinm.",
1583 RLWNM: "rlwnm",
1584 RLWNMCC: "rlwnm.",
1585 RLWIMI: "rlwimi",
1586 RLWIMICC: "rlwimi.",
1587 RLDICL: "rldicl",
1588 RLDICLCC: "rldicl.",
1589 RLDICR: "rldicr",
1590 RLDICRCC: "rldicr.",
1591 RLDIC: "rldic",
1592 RLDICCC: "rldic.",
1593 RLDCL: "rldcl",
1594 RLDCLCC: "rldcl.",
1595 RLDCR: "rldcr",
1596 RLDCRCC: "rldcr.",
1597 RLDIMI: "rldimi",
1598 RLDIMICC: "rldimi.",
1599 SLW: "slw",
1600 SLWCC: "slw.",
1601 SRW: "srw",
1602 SRWCC: "srw.",
1603 SRAWI: "srawi",
1604 SRAWICC: "srawi.",
1605 SRAW: "sraw",
1606 SRAWCC: "sraw.",
1607 SLD: "sld",
1608 SLDCC: "sld.",
1609 SRD: "srd",
1610 SRDCC: "srd.",
1611 SRADI: "sradi",
1612 SRADICC: "sradi.",
1613 SRAD: "srad",
1614 SRADCC: "srad.",
1615 CDTBCD: "cdtbcd",
1616 CBCDTD: "cbcdtd",
1617 ADDG6S: "addg6s",
1618 MTSPR: "mtspr",
1619 MFSPR: "mfspr",
1620 MTCRF: "mtcrf",
1621 MFCR: "mfcr",
1622 MTSLE: "mtsle",
1623 MFVSRD: "mfvsrd",
1624 MFVSRWZ: "mfvsrwz",
1625 MTVSRD: "mtvsrd",
1626 MTVSRWA: "mtvsrwa",
1627 MTVSRWZ: "mtvsrwz",
1628 MTOCRF: "mtocrf",
1629 MFOCRF: "mfocrf",
1630 MCRXR: "mcrxr",
1631 MTDCRUX: "mtdcrux",
1632 MFDCRUX: "mfdcrux",
1633 LFS: "lfs",
1634 LFSU: "lfsu",
1635 LFSX: "lfsx",
1636 LFSUX: "lfsux",
1637 LFD: "lfd",
1638 LFDU: "lfdu",
1639 LFDX: "lfdx",
1640 LFDUX: "lfdux",
1641 LFIWAX: "lfiwax",
1642 LFIWZX: "lfiwzx",
1643 STFS: "stfs",
1644 STFSU: "stfsu",
1645 STFSX: "stfsx",
1646 STFSUX: "stfsux",
1647 STFD: "stfd",
1648 STFDU: "stfdu",
1649 STFDX: "stfdx",
1650 STFDUX: "stfdux",
1651 STFIWX: "stfiwx",
1652 LFDP: "lfdp",
1653 LFDPX: "lfdpx",
1654 STFDP: "stfdp",
1655 STFDPX: "stfdpx",
1656 FMR: "fmr",
1657 FMRCC: "fmr.",
1658 FABS: "fabs",
1659 FABSCC: "fabs.",
1660 FNABS: "fnabs",
1661 FNABSCC: "fnabs.",
1662 FNEG: "fneg",
1663 FNEGCC: "fneg.",
1664 FCPSGN: "fcpsgn",
1665 FCPSGNCC: "fcpsgn.",
1666 FMRGEW: "fmrgew",
1667 FMRGOW: "fmrgow",
1668 FADD: "fadd",
1669 FADDCC: "fadd.",
1670 FADDS: "fadds",
1671 FADDSCC: "fadds.",
1672 FSUB: "fsub",
1673 FSUBCC: "fsub.",
1674 FSUBS: "fsubs",
1675 FSUBSCC: "fsubs.",
1676 FMUL: "fmul",
1677 FMULCC: "fmul.",
1678 FMULS: "fmuls",
1679 FMULSCC: "fmuls.",
1680 FDIV: "fdiv",
1681 FDIVCC: "fdiv.",
1682 FDIVS: "fdivs",
1683 FDIVSCC: "fdivs.",
1684 FSQRT: "fsqrt",
1685 FSQRTCC: "fsqrt.",
1686 FSQRTS: "fsqrts",
1687 FSQRTSCC: "fsqrts.",
1688 FRE: "fre",
1689 FRECC: "fre.",
1690 FRES: "fres",
1691 FRESCC: "fres.",
1692 FRSQRTE: "frsqrte",
1693 FRSQRTECC: "frsqrte.",
1694 FRSQRTES: "frsqrtes",
1695 FRSQRTESCC: "frsqrtes.",
1696 FTDIV: "ftdiv",
1697 FTSQRT: "ftsqrt",
1698 FMADD: "fmadd",
1699 FMADDCC: "fmadd.",
1700 FMADDS: "fmadds",
1701 FMADDSCC: "fmadds.",
1702 FMSUB: "fmsub",
1703 FMSUBCC: "fmsub.",
1704 FMSUBS: "fmsubs",
1705 FMSUBSCC: "fmsubs.",
1706 FNMADD: "fnmadd",
1707 FNMADDCC: "fnmadd.",
1708 FNMADDS: "fnmadds",
1709 FNMADDSCC: "fnmadds.",
1710 FNMSUB: "fnmsub",
1711 FNMSUBCC: "fnmsub.",
1712 FNMSUBS: "fnmsubs",
1713 FNMSUBSCC: "fnmsubs.",
1714 FRSP: "frsp",
1715 FRSPCC: "frsp.",
1716 FCTID: "fctid",
1717 FCTIDCC: "fctid.",
1718 FCTIDZ: "fctidz",
1719 FCTIDZCC: "fctidz.",
1720 FCTIDU: "fctidu",
1721 FCTIDUCC: "fctidu.",
1722 FCTIDUZ: "fctiduz",
1723 FCTIDUZCC: "fctiduz.",
1724 FCTIW: "fctiw",
1725 FCTIWCC: "fctiw.",
1726 FCTIWZ: "fctiwz",
1727 FCTIWZCC: "fctiwz.",
1728 FCTIWU: "fctiwu",
1729 FCTIWUCC: "fctiwu.",
1730 FCTIWUZ: "fctiwuz",
1731 FCTIWUZCC: "fctiwuz.",
1732 FCFID: "fcfid",
1733 FCFIDCC: "fcfid.",
1734 FCFIDU: "fcfidu",
1735 FCFIDUCC: "fcfidu.",
1736 FCFIDS: "fcfids",
1737 FCFIDSCC: "fcfids.",
1738 FCFIDUS: "fcfidus",
1739 FCFIDUSCC: "fcfidus.",
1740 FRIN: "frin",
1741 FRINCC: "frin.",
1742 FRIZ: "friz",
1743 FRIZCC: "friz.",
1744 FRIP: "frip",
1745 FRIPCC: "frip.",
1746 FRIM: "frim",
1747 FRIMCC: "frim.",
1748 FCMPU: "fcmpu",
1749 FCMPO: "fcmpo",
1750 FSEL: "fsel",
1751 FSELCC: "fsel.",
1752 MFFS: "mffs",
1753 MFFSCC: "mffs.",
1754 MCRFS: "mcrfs",
1755 MTFSFI: "mtfsfi",
1756 MTFSFICC: "mtfsfi.",
1757 MTFSF: "mtfsf",
1758 MTFSFCC: "mtfsf.",
1759 MTFSB0: "mtfsb0",
1760 MTFSB0CC: "mtfsb0.",
1761 MTFSB1: "mtfsb1",
1762 MTFSB1CC: "mtfsb1.",
1763 LVEBX: "lvebx",
1764 LVEHX: "lvehx",
1765 LVEWX: "lvewx",
1766 LVX: "lvx",
1767 LVXL: "lvxl",
1768 STVEBX: "stvebx",
1769 STVEHX: "stvehx",
1770 STVEWX: "stvewx",
1771 STVX: "stvx",
1772 STVXL: "stvxl",
1773 LVSL: "lvsl",
1774 LVSR: "lvsr",
1775 VPKPX: "vpkpx",
1776 VPKSDSS: "vpksdss",
1777 VPKSDUS: "vpksdus",
1778 VPKSHSS: "vpkshss",
1779 VPKSHUS: "vpkshus",
1780 VPKSWSS: "vpkswss",
1781 VPKSWUS: "vpkswus",
1782 VPKUDUM: "vpkudum",
1783 VPKUDUS: "vpkudus",
1784 VPKUHUM: "vpkuhum",
1785 VPKUHUS: "vpkuhus",
1786 VPKUWUM: "vpkuwum",
1787 VPKUWUS: "vpkuwus",
1788 VUPKHPX: "vupkhpx",
1789 VUPKLPX: "vupklpx",
1790 VUPKHSB: "vupkhsb",
1791 VUPKHSH: "vupkhsh",
1792 VUPKHSW: "vupkhsw",
1793 VUPKLSB: "vupklsb",
1794 VUPKLSH: "vupklsh",
1795 VUPKLSW: "vupklsw",
1796 VMRGHB: "vmrghb",
1797 VMRGHH: "vmrghh",
1798 VMRGLB: "vmrglb",
1799 VMRGLH: "vmrglh",
1800 VMRGHW: "vmrghw",
1801 VMRGLW: "vmrglw",
1802 VMRGEW: "vmrgew",
1803 VMRGOW: "vmrgow",
1804 VSPLTB: "vspltb",
1805 VSPLTH: "vsplth",
1806 VSPLTW: "vspltw",
1807 VSPLTISB: "vspltisb",
1808 VSPLTISH: "vspltish",
1809 VSPLTISW: "vspltisw",
1810 VPERM: "vperm",
1811 VSEL: "vsel",
1812 VSL: "vsl",
1813 VSLDOI: "vsldoi",
1814 VSLO: "vslo",
1815 VSR: "vsr",
1816 VSRO: "vsro",
1817 VADDCUW: "vaddcuw",
1818 VADDSBS: "vaddsbs",
1819 VADDSHS: "vaddshs",
1820 VADDSWS: "vaddsws",
1821 VADDUBM: "vaddubm",
1822 VADDUDM: "vaddudm",
1823 VADDUHM: "vadduhm",
1824 VADDUWM: "vadduwm",
1825 VADDUBS: "vaddubs",
1826 VADDUHS: "vadduhs",
1827 VADDUWS: "vadduws",
1828 VADDUQM: "vadduqm",
1829 VADDEUQM: "vaddeuqm",
1830 VADDCUQ: "vaddcuq",
1831 VADDECUQ: "vaddecuq",
1832 VSUBCUW: "vsubcuw",
1833 VSUBSBS: "vsubsbs",
1834 VSUBSHS: "vsubshs",
1835 VSUBSWS: "vsubsws",
1836 VSUBUBM: "vsububm",
1837 VSUBUDM: "vsubudm",
1838 VSUBUHM: "vsubuhm",
1839 VSUBUWM: "vsubuwm",
1840 VSUBUBS: "vsububs",
1841 VSUBUHS: "vsubuhs",
1842 VSUBUWS: "vsubuws",
1843 VSUBUQM: "vsubuqm",
1844 VSUBEUQM: "vsubeuqm",
1845 VSUBCUQ: "vsubcuq",
1846 VSUBECUQ: "vsubecuq",
1847 VMULESB: "vmulesb",
1848 VMULEUB: "vmuleub",
1849 VMULOSB: "vmulosb",
1850 VMULOUB: "vmuloub",
1851 VMULESH: "vmulesh",
1852 VMULEUH: "vmuleuh",
1853 VMULOSH: "vmulosh",
1854 VMULOUH: "vmulouh",
1855 VMULESW: "vmulesw",
1856 VMULEUW: "vmuleuw",
1857 VMULOSW: "vmulosw",
1858 VMULOUW: "vmulouw",
1859 VMULUWM: "vmuluwm",
1860 VMHADDSHS: "vmhaddshs",
1861 VMHRADDSHS: "vmhraddshs",
1862 VMLADDUHM: "vmladduhm",
1863 VMSUMUBM: "vmsumubm",
1864 VMSUMMBM: "vmsummbm",
1865 VMSUMSHM: "vmsumshm",
1866 VMSUMSHS: "vmsumshs",
1867 VMSUMUHM: "vmsumuhm",
1868 VMSUMUHS: "vmsumuhs",
1869 VSUMSWS: "vsumsws",
1870 VSUM2SWS: "vsum2sws",
1871 VSUM4SBS: "vsum4sbs",
1872 VSUM4SHS: "vsum4shs",
1873 VSUM4UBS: "vsum4ubs",
1874 VAVGSB: "vavgsb",
1875 VAVGSH: "vavgsh",
1876 VAVGSW: "vavgsw",
1877 VAVGUB: "vavgub",
1878 VAVGUW: "vavguw",
1879 VAVGUH: "vavguh",
1880 VMAXSB: "vmaxsb",
1881 VMAXSD: "vmaxsd",
1882 VMAXUB: "vmaxub",
1883 VMAXUD: "vmaxud",
1884 VMAXSH: "vmaxsh",
1885 VMAXSW: "vmaxsw",
1886 VMAXUH: "vmaxuh",
1887 VMAXUW: "vmaxuw",
1888 VMINSB: "vminsb",
1889 VMINSD: "vminsd",
1890 VMINUB: "vminub",
1891 VMINUD: "vminud",
1892 VMINSH: "vminsh",
1893 VMINSW: "vminsw",
1894 VMINUH: "vminuh",
1895 VMINUW: "vminuw",
1896 VCMPEQUB: "vcmpequb",
1897 VCMPEQUBCC: "vcmpequb.",
1898 VCMPEQUH: "vcmpequh",
1899 VCMPEQUHCC: "vcmpequh.",
1900 VCMPEQUW: "vcmpequw",
1901 VCMPEQUWCC: "vcmpequw.",
1902 VCMPEQUD: "vcmpequd",
1903 VCMPEQUDCC: "vcmpequd.",
1904 VCMPGTSB: "vcmpgtsb",
1905 VCMPGTSBCC: "vcmpgtsb.",
1906 VCMPGTSD: "vcmpgtsd",
1907 VCMPGTSDCC: "vcmpgtsd.",
1908 VCMPGTSH: "vcmpgtsh",
1909 VCMPGTSHCC: "vcmpgtsh.",
1910 VCMPGTSW: "vcmpgtsw",
1911 VCMPGTSWCC: "vcmpgtsw.",
1912 VCMPGTUB: "vcmpgtub",
1913 VCMPGTUBCC: "vcmpgtub.",
1914 VCMPGTUD: "vcmpgtud",
1915 VCMPGTUDCC: "vcmpgtud.",
1916 VCMPGTUH: "vcmpgtuh",
1917 VCMPGTUHCC: "vcmpgtuh.",
1918 VCMPGTUW: "vcmpgtuw",
1919 VCMPGTUWCC: "vcmpgtuw.",
1920 VAND: "vand",
1921 VANDC: "vandc",
1922 VEQV: "veqv",
1923 VNAND: "vnand",
1924 VORC: "vorc",
1925 VNOR: "vnor",
1926 VOR: "vor",
1927 VXOR: "vxor",
1928 VRLB: "vrlb",
1929 VRLH: "vrlh",
1930 VRLW: "vrlw",
1931 VRLD: "vrld",
1932 VSLB: "vslb",
1933 VSLH: "vslh",
1934 VSLW: "vslw",
1935 VSLD: "vsld",
1936 VSRB: "vsrb",
1937 VSRH: "vsrh",
1938 VSRW: "vsrw",
1939 VSRD: "vsrd",
1940 VSRAB: "vsrab",
1941 VSRAH: "vsrah",
1942 VSRAW: "vsraw",
1943 VSRAD: "vsrad",
1944 VADDFP: "vaddfp",
1945 VSUBFP: "vsubfp",
1946 VMADDFP: "vmaddfp",
1947 VNMSUBFP: "vnmsubfp",
1948 VMAXFP: "vmaxfp",
1949 VMINFP: "vminfp",
1950 VCTSXS: "vctsxs",
1951 VCTUXS: "vctuxs",
1952 VCFSX: "vcfsx",
1953 VCFUX: "vcfux",
1954 VRFIM: "vrfim",
1955 VRFIN: "vrfin",
1956 VRFIP: "vrfip",
1957 VRFIZ: "vrfiz",
1958 VCMPBFP: "vcmpbfp",
1959 VCMPBFPCC: "vcmpbfp.",
1960 VCMPEQFP: "vcmpeqfp",
1961 VCMPEQFPCC: "vcmpeqfp.",
1962 VCMPGEFP: "vcmpgefp",
1963 VCMPGEFPCC: "vcmpgefp.",
1964 VCMPGTFP: "vcmpgtfp",
1965 VCMPGTFPCC: "vcmpgtfp.",
1966 VEXPTEFP: "vexptefp",
1967 VLOGEFP: "vlogefp",
1968 VREFP: "vrefp",
1969 VRSQRTEFP: "vrsqrtefp",
1970 VCIPHER: "vcipher",
1971 VCIPHERLAST: "vcipherlast",
1972 VNCIPHER: "vncipher",
1973 VNCIPHERLAST: "vncipherlast",
1974 VSBOX: "vsbox",
1975 VSHASIGMAD: "vshasigmad",
1976 VSHASIGMAW: "vshasigmaw",
1977 VPMSUMB: "vpmsumb",
1978 VPMSUMD: "vpmsumd",
1979 VPMSUMH: "vpmsumh",
1980 VPMSUMW: "vpmsumw",
1981 VPERMXOR: "vpermxor",
1982 VGBBD: "vgbbd",
1983 VCLZB: "vclzb",
1984 VCLZH: "vclzh",
1985 VCLZW: "vclzw",
1986 VCLZD: "vclzd",
1987 VPOPCNTB: "vpopcntb",
1988 VPOPCNTD: "vpopcntd",
1989 VPOPCNTH: "vpopcnth",
1990 VPOPCNTW: "vpopcntw",
1991 VBPERMQ: "vbpermq",
1992 BCDADDCC: "bcdadd.",
1993 BCDSUBCC: "bcdsub.",
1994 MTVSCR: "mtvscr",
1995 MFVSCR: "mfvscr",
1996 DADD: "dadd",
1997 DADDCC: "dadd.",
1998 DSUB: "dsub",
1999 DSUBCC: "dsub.",
2000 DMUL: "dmul",
2001 DMULCC: "dmul.",
2002 DDIV: "ddiv",
2003 DDIVCC: "ddiv.",
2004 DCMPU: "dcmpu",
2005 DCMPO: "dcmpo",
2006 DTSTDC: "dtstdc",
2007 DTSTDG: "dtstdg",
2008 DTSTEX: "dtstex",
2009 DTSTSF: "dtstsf",
2010 DQUAI: "dquai",
2011 DQUAICC: "dquai.",
2012 DQUA: "dqua",
2013 DQUACC: "dqua.",
2014 DRRND: "drrnd",
2015 DRRNDCC: "drrnd.",
2016 DRINTX: "drintx",
2017 DRINTXCC: "drintx.",
2018 DRINTN: "drintn",
2019 DRINTNCC: "drintn.",
2020 DCTDP: "dctdp",
2021 DCTDPCC: "dctdp.",
2022 DCTQPQ: "dctqpq",
2023 DCTQPQCC: "dctqpq.",
2024 DRSP: "drsp",
2025 DRSPCC: "drsp.",
2026 DRDPQ: "drdpq",
2027 DRDPQCC: "drdpq.",
2028 DCFFIX: "dcffix",
2029 DCFFIXCC: "dcffix.",
2030 DCFFIXQ: "dcffixq",
2031 DCFFIXQCC: "dcffixq.",
2032 DCTFIX: "dctfix",
2033 DCTFIXCC: "dctfix.",
2034 DDEDPD: "ddedpd",
2035 DDEDPDCC: "ddedpd.",
2036 DENBCD: "denbcd",
2037 DENBCDCC: "denbcd.",
2038 DXEX: "dxex",
2039 DXEXCC: "dxex.",
2040 DIEX: "diex",
2041 DIEXCC: "diex.",
2042 DSCLI: "dscli",
2043 DSCLICC: "dscli.",
2044 DSCRI: "dscri",
2045 DSCRICC: "dscri.",
2046 LXSDX: "lxsdx",
2047 LXSIWAX: "lxsiwax",
2048 LXSIWZX: "lxsiwzx",
2049 LXSSPX: "lxsspx",
2050 LXVD2X: "lxvd2x",
2051 LXVDSX: "lxvdsx",
2052 LXVW4X: "lxvw4x",
2053 STXSDX: "stxsdx",
2054 STXSIWX: "stxsiwx",
2055 STXSSPX: "stxsspx",
2056 STXVD2X: "stxvd2x",
2057 STXVW4X: "stxvw4x",
2058 XSABSDP: "xsabsdp",
2059 XSADDDP: "xsadddp",
2060 XSADDSP: "xsaddsp",
2061 XSCMPODP: "xscmpodp",
2062 XSCMPUDP: "xscmpudp",
2063 XSCPSGNDP: "xscpsgndp",
2064 XSCVDPSP: "xscvdpsp",
2065 XSCVDPSPN: "xscvdpspn",
2066 XSCVDPSXDS: "xscvdpsxds",
2067 XSCVDPSXWS: "xscvdpsxws",
2068 XSCVDPUXDS: "xscvdpuxds",
2069 XSCVDPUXWS: "xscvdpuxws",
2070 XSCVSPDP: "xscvspdp",
2071 XSCVSPDPN: "xscvspdpn",
2072 XSCVSXDDP: "xscvsxddp",
2073 XSCVSXDSP: "xscvsxdsp",
2074 XSCVUXDDP: "xscvuxddp",
2075 XSCVUXDSP: "xscvuxdsp",
2076 XSDIVDP: "xsdivdp",
2077 XSDIVSP: "xsdivsp",
2078 XSMADDADP: "xsmaddadp",
2079 XSMADDASP: "xsmaddasp",
2080 XSMAXDP: "xsmaxdp",
2081 XSMINDP: "xsmindp",
2082 XSMSUBADP: "xsmsubadp",
2083 XSMSUBASP: "xsmsubasp",
2084 XSMULDP: "xsmuldp",
2085 XSMULSP: "xsmulsp",
2086 XSNABSDP: "xsnabsdp",
2087 XSNEGDP: "xsnegdp",
2088 XSNMADDADP: "xsnmaddadp",
2089 XSNMADDASP: "xsnmaddasp",
2090 XSNMSUBADP: "xsnmsubadp",
2091 XSNMSUBASP: "xsnmsubasp",
2092 XSRDPI: "xsrdpi",
2093 XSRDPIC: "xsrdpic",
2094 XSRDPIM: "xsrdpim",
2095 XSRDPIP: "xsrdpip",
2096 XSRDPIZ: "xsrdpiz",
2097 XSREDP: "xsredp",
2098 XSRESP: "xsresp",
2099 XSRSP: "xsrsp",
2100 XSRSQRTEDP: "xsrsqrtedp",
2101 XSRSQRTESP: "xsrsqrtesp",
2102 XSSQRTDP: "xssqrtdp",
2103 XSSQRTSP: "xssqrtsp",
2104 XSSUBDP: "xssubdp",
2105 XSSUBSP: "xssubsp",
2106 XSTDIVDP: "xstdivdp",
2107 XSTSQRTDP: "xstsqrtdp",
2108 XVABSDP: "xvabsdp",
2109 XVABSSP: "xvabssp",
2110 XVADDDP: "xvadddp",
2111 XVADDSP: "xvaddsp",
2112 XVCMPEQDP: "xvcmpeqdp",
2113 XVCMPEQDPCC: "xvcmpeqdp.",
2114 XVCMPEQSP: "xvcmpeqsp",
2115 XVCMPEQSPCC: "xvcmpeqsp.",
2116 XVCMPGEDP: "xvcmpgedp",
2117 XVCMPGEDPCC: "xvcmpgedp.",
2118 XVCMPGESP: "xvcmpgesp",
2119 XVCMPGESPCC: "xvcmpgesp.",
2120 XVCMPGTDP: "xvcmpgtdp",
2121 XVCMPGTDPCC: "xvcmpgtdp.",
2122 XVCMPGTSP: "xvcmpgtsp",
2123 XVCMPGTSPCC: "xvcmpgtsp.",
2124 XVCPSGNDP: "xvcpsgndp",
2125 XVCPSGNSP: "xvcpsgnsp",
2126 XVCVDPSP: "xvcvdpsp",
2127 XVCVDPSXDS: "xvcvdpsxds",
2128 XVCVDPSXWS: "xvcvdpsxws",
2129 XVCVDPUXDS: "xvcvdpuxds",
2130 XVCVDPUXWS: "xvcvdpuxws",
2131 XVCVSPDP: "xvcvspdp",
2132 XVCVSPSXDS: "xvcvspsxds",
2133 XVCVSPSXWS: "xvcvspsxws",
2134 XVCVSPUXDS: "xvcvspuxds",
2135 XVCVSPUXWS: "xvcvspuxws",
2136 XVCVSXDDP: "xvcvsxddp",
2137 XVCVSXDSP: "xvcvsxdsp",
2138 XVCVSXWDP: "xvcvsxwdp",
2139 XVCVSXWSP: "xvcvsxwsp",
2140 XVCVUXDDP: "xvcvuxddp",
2141 XVCVUXDSP: "xvcvuxdsp",
2142 XVCVUXWDP: "xvcvuxwdp",
2143 XVCVUXWSP: "xvcvuxwsp",
2144 XVDIVDP: "xvdivdp",
2145 XVDIVSP: "xvdivsp",
2146 XVMADDADP: "xvmaddadp",
2147 XVMADDASP: "xvmaddasp",
2148 XVMAXDP: "xvmaxdp",
2149 XVMAXSP: "xvmaxsp",
2150 XVMINDP: "xvmindp",
2151 XVMINSP: "xvminsp",
2152 XVMSUBADP: "xvmsubadp",
2153 XVMSUBASP: "xvmsubasp",
2154 XVMULDP: "xvmuldp",
2155 XVMULSP: "xvmulsp",
2156 XVNABSDP: "xvnabsdp",
2157 XVNABSSP: "xvnabssp",
2158 XVNEGDP: "xvnegdp",
2159 XVNEGSP: "xvnegsp",
2160 XVNMADDADP: "xvnmaddadp",
2161 XVNMADDASP: "xvnmaddasp",
2162 XVNMSUBADP: "xvnmsubadp",
2163 XVNMSUBASP: "xvnmsubasp",
2164 XVRDPI: "xvrdpi",
2165 XVRDPIC: "xvrdpic",
2166 XVRDPIM: "xvrdpim",
2167 XVRDPIP: "xvrdpip",
2168 XVRDPIZ: "xvrdpiz",
2169 XVREDP: "xvredp",
2170 XVRESP: "xvresp",
2171 XVRSPI: "xvrspi",
2172 XVRSPIC: "xvrspic",
2173 XVRSPIM: "xvrspim",
2174 XVRSPIP: "xvrspip",
2175 XVRSPIZ: "xvrspiz",
2176 XVRSQRTEDP: "xvrsqrtedp",
2177 XVRSQRTESP: "xvrsqrtesp",
2178 XVSQRTDP: "xvsqrtdp",
2179 XVSQRTSP: "xvsqrtsp",
2180 XVSUBDP: "xvsubdp",
2181 XVSUBSP: "xvsubsp",
2182 XVTDIVDP: "xvtdivdp",
2183 XVTDIVSP: "xvtdivsp",
2184 XVTSQRTDP: "xvtsqrtdp",
2185 XVTSQRTSP: "xvtsqrtsp",
2186 XXLAND: "xxland",
2187 XXLANDC: "xxlandc",
2188 XXLEQV: "xxleqv",
2189 XXLNAND: "xxlnand",
2190 XXLORC: "xxlorc",
2191 XXLNOR: "xxlnor",
2192 XXLOR: "xxlor",
2193 XXLXOR: "xxlxor",
2194 XXMRGHW: "xxmrghw",
2195 XXMRGLW: "xxmrglw",
2196 XXPERMDI: "xxpermdi",
2197 XXSEL: "xxsel",
2198 XXSLDWI: "xxsldwi",
2199 XXSPLTW: "xxspltw",
2200 BRINC: "brinc",
2201 EVABS: "evabs",
2202 EVADDIW: "evaddiw",
2203 EVADDSMIAAW: "evaddsmiaaw",
2204 EVADDSSIAAW: "evaddssiaaw",
2205 EVADDUMIAAW: "evaddumiaaw",
2206 EVADDUSIAAW: "evaddusiaaw",
2207 EVADDW: "evaddw",
2208 EVAND: "evand",
2209 EVCMPEQ: "evcmpeq",
2210 EVANDC: "evandc",
2211 EVCMPGTS: "evcmpgts",
2212 EVCMPGTU: "evcmpgtu",
2213 EVCMPLTU: "evcmpltu",
2214 EVCMPLTS: "evcmplts",
2215 EVCNTLSW: "evcntlsw",
2216 EVCNTLZW: "evcntlzw",
2217 EVDIVWS: "evdivws",
2218 EVDIVWU: "evdivwu",
2219 EVEQV: "eveqv",
2220 EVEXTSB: "evextsb",
2221 EVEXTSH: "evextsh",
2222 EVLDD: "evldd",
2223 EVLDH: "evldh",
2224 EVLDDX: "evlddx",
2225 EVLDHX: "evldhx",
2226 EVLDW: "evldw",
2227 EVLHHESPLAT: "evlhhesplat",
2228 EVLDWX: "evldwx",
2229 EVLHHESPLATX: "evlhhesplatx",
2230 EVLHHOSSPLAT: "evlhhossplat",
2231 EVLHHOUSPLAT: "evlhhousplat",
2232 EVLHHOSSPLATX: "evlhhossplatx",
2233 EVLHHOUSPLATX: "evlhhousplatx",
2234 EVLWHE: "evlwhe",
2235 EVLWHOS: "evlwhos",
2236 EVLWHEX: "evlwhex",
2237 EVLWHOSX: "evlwhosx",
2238 EVLWHOU: "evlwhou",
2239 EVLWHSPLAT: "evlwhsplat",
2240 EVLWHOUX: "evlwhoux",
2241 EVLWHSPLATX: "evlwhsplatx",
2242 EVLWWSPLAT: "evlwwsplat",
2243 EVMERGEHI: "evmergehi",
2244 EVLWWSPLATX: "evlwwsplatx",
2245 EVMERGELO: "evmergelo",
2246 EVMERGEHILO: "evmergehilo",
2247 EVMHEGSMFAA: "evmhegsmfaa",
2248 EVMERGELOHI: "evmergelohi",
2249 EVMHEGSMFAN: "evmhegsmfan",
2250 EVMHEGSMIAA: "evmhegsmiaa",
2251 EVMHEGUMIAA: "evmhegumiaa",
2252 EVMHEGSMIAN: "evmhegsmian",
2253 EVMHEGUMIAN: "evmhegumian",
2254 EVMHESMF: "evmhesmf",
2255 EVMHESMFAAW: "evmhesmfaaw",
2256 EVMHESMFA: "evmhesmfa",
2257 EVMHESMFANW: "evmhesmfanw",
2258 EVMHESMI: "evmhesmi",
2259 EVMHESMIAAW: "evmhesmiaaw",
2260 EVMHESMIA: "evmhesmia",
2261 EVMHESMIANW: "evmhesmianw",
2262 EVMHESSF: "evmhessf",
2263 EVMHESSFA: "evmhessfa",
2264 EVMHESSFAAW: "evmhessfaaw",
2265 EVMHESSFANW: "evmhessfanw",
2266 EVMHESSIAAW: "evmhessiaaw",
2267 EVMHESSIANW: "evmhessianw",
2268 EVMHEUMI: "evmheumi",
2269 EVMHEUMIAAW: "evmheumiaaw",
2270 EVMHEUMIA: "evmheumia",
2271 EVMHEUMIANW: "evmheumianw",
2272 EVMHEUSIAAW: "evmheusiaaw",
2273 EVMHEUSIANW: "evmheusianw",
2274 EVMHOGSMFAA: "evmhogsmfaa",
2275 EVMHOGSMIAA: "evmhogsmiaa",
2276 EVMHOGSMFAN: "evmhogsmfan",
2277 EVMHOGSMIAN: "evmhogsmian",
2278 EVMHOGUMIAA: "evmhogumiaa",
2279 EVMHOSMF: "evmhosmf",
2280 EVMHOGUMIAN: "evmhogumian",
2281 EVMHOSMFA: "evmhosmfa",
2282 EVMHOSMFAAW: "evmhosmfaaw",
2283 EVMHOSMI: "evmhosmi",
2284 EVMHOSMFANW: "evmhosmfanw",
2285 EVMHOSMIA: "evmhosmia",
2286 EVMHOSMIAAW: "evmhosmiaaw",
2287 EVMHOSMIANW: "evmhosmianw",
2288 EVMHOSSF: "evmhossf",
2289 EVMHOSSFA: "evmhossfa",
2290 EVMHOSSFAAW: "evmhossfaaw",
2291 EVMHOSSFANW: "evmhossfanw",
2292 EVMHOSSIAAW: "evmhossiaaw",
2293 EVMHOUMI: "evmhoumi",
2294 EVMHOSSIANW: "evmhossianw",
2295 EVMHOUMIA: "evmhoumia",
2296 EVMHOUMIAAW: "evmhoumiaaw",
2297 EVMHOUSIAAW: "evmhousiaaw",
2298 EVMHOUMIANW: "evmhoumianw",
2299 EVMHOUSIANW: "evmhousianw",
2300 EVMRA: "evmra",
2301 EVMWHSMF: "evmwhsmf",
2302 EVMWHSMI: "evmwhsmi",
2303 EVMWHSMFA: "evmwhsmfa",
2304 EVMWHSMIA: "evmwhsmia",
2305 EVMWHSSF: "evmwhssf",
2306 EVMWHUMI: "evmwhumi",
2307 EVMWHSSFA: "evmwhssfa",
2308 EVMWHUMIA: "evmwhumia",
2309 EVMWLSMIAAW: "evmwlsmiaaw",
2310 EVMWLSSIAAW: "evmwlssiaaw",
2311 EVMWLSMIANW: "evmwlsmianw",
2312 EVMWLSSIANW: "evmwlssianw",
2313 EVMWLUMI: "evmwlumi",
2314 EVMWLUMIAAW: "evmwlumiaaw",
2315 EVMWLUMIA: "evmwlumia",
2316 EVMWLUMIANW: "evmwlumianw",
2317 EVMWLUSIAAW: "evmwlusiaaw",
2318 EVMWSMF: "evmwsmf",
2319 EVMWLUSIANW: "evmwlusianw",
2320 EVMWSMFA: "evmwsmfa",
2321 EVMWSMFAA: "evmwsmfaa",
2322 EVMWSMI: "evmwsmi",
2323 EVMWSMIAA: "evmwsmiaa",
2324 EVMWSMFAN: "evmwsmfan",
2325 EVMWSMIA: "evmwsmia",
2326 EVMWSMIAN: "evmwsmian",
2327 EVMWSSF: "evmwssf",
2328 EVMWSSFA: "evmwssfa",
2329 EVMWSSFAA: "evmwssfaa",
2330 EVMWUMI: "evmwumi",
2331 EVMWSSFAN: "evmwssfan",
2332 EVMWUMIA: "evmwumia",
2333 EVMWUMIAA: "evmwumiaa",
2334 EVNAND: "evnand",
2335 EVMWUMIAN: "evmwumian",
2336 EVNEG: "evneg",
2337 EVNOR: "evnor",
2338 EVORC: "evorc",
2339 EVOR: "evor",
2340 EVRLW: "evrlw",
2341 EVRLWI: "evrlwi",
2342 EVSEL: "evsel",
2343 EVRNDW: "evrndw",
2344 EVSLW: "evslw",
2345 EVSPLATFI: "evsplatfi",
2346 EVSRWIS: "evsrwis",
2347 EVSLWI: "evslwi",
2348 EVSPLATI: "evsplati",
2349 EVSRWIU: "evsrwiu",
2350 EVSRWS: "evsrws",
2351 EVSTDD: "evstdd",
2352 EVSRWU: "evsrwu",
2353 EVSTDDX: "evstddx",
2354 EVSTDH: "evstdh",
2355 EVSTDW: "evstdw",
2356 EVSTDHX: "evstdhx",
2357 EVSTDWX: "evstdwx",
2358 EVSTWHE: "evstwhe",
2359 EVSTWHO: "evstwho",
2360 EVSTWWE: "evstwwe",
2361 EVSTWHEX: "evstwhex",
2362 EVSTWHOX: "evstwhox",
2363 EVSTWWEX: "evstwwex",
2364 EVSTWWO: "evstwwo",
2365 EVSUBFSMIAAW: "evsubfsmiaaw",
2366 EVSTWWOX: "evstwwox",
2367 EVSUBFSSIAAW: "evsubfssiaaw",
2368 EVSUBFUMIAAW: "evsubfumiaaw",
2369 EVSUBFUSIAAW: "evsubfusiaaw",
2370 EVSUBFW: "evsubfw",
2371 EVSUBIFW: "evsubifw",
2372 EVXOR: "evxor",
2373 EVFSABS: "evfsabs",
2374 EVFSNABS: "evfsnabs",
2375 EVFSNEG: "evfsneg",
2376 EVFSADD: "evfsadd",
2377 EVFSMUL: "evfsmul",
2378 EVFSSUB: "evfssub",
2379 EVFSDIV: "evfsdiv",
2380 EVFSCMPGT: "evfscmpgt",
2381 EVFSCMPLT: "evfscmplt",
2382 EVFSCMPEQ: "evfscmpeq",
2383 EVFSTSTGT: "evfststgt",
2384 EVFSTSTLT: "evfststlt",
2385 EVFSTSTEQ: "evfststeq",
2386 EVFSCFSI: "evfscfsi",
2387 EVFSCFSF: "evfscfsf",
2388 EVFSCFUI: "evfscfui",
2389 EVFSCFUF: "evfscfuf",
2390 EVFSCTSI: "evfsctsi",
2391 EVFSCTUI: "evfsctui",
2392 EVFSCTSIZ: "evfsctsiz",
2393 EVFSCTUIZ: "evfsctuiz",
2394 EVFSCTSF: "evfsctsf",
2395 EVFSCTUF: "evfsctuf",
2396 EFSABS: "efsabs",
2397 EFSNEG: "efsneg",
2398 EFSNABS: "efsnabs",
2399 EFSADD: "efsadd",
2400 EFSMUL: "efsmul",
2401 EFSSUB: "efssub",
2402 EFSDIV: "efsdiv",
2403 EFSCMPGT: "efscmpgt",
2404 EFSCMPLT: "efscmplt",
2405 EFSCMPEQ: "efscmpeq",
2406 EFSTSTGT: "efststgt",
2407 EFSTSTLT: "efststlt",
2408 EFSTSTEQ: "efststeq",
2409 EFSCFSI: "efscfsi",
2410 EFSCFSF: "efscfsf",
2411 EFSCTSI: "efsctsi",
2412 EFSCFUI: "efscfui",
2413 EFSCFUF: "efscfuf",
2414 EFSCTUI: "efsctui",
2415 EFSCTSIZ: "efsctsiz",
2416 EFSCTSF: "efsctsf",
2417 EFSCTUIZ: "efsctuiz",
2418 EFSCTUF: "efsctuf",
2419 EFDABS: "efdabs",
2420 EFDNEG: "efdneg",
2421 EFDNABS: "efdnabs",
2422 EFDADD: "efdadd",
2423 EFDMUL: "efdmul",
2424 EFDSUB: "efdsub",
2425 EFDDIV: "efddiv",
2426 EFDCMPGT: "efdcmpgt",
2427 EFDCMPEQ: "efdcmpeq",
2428 EFDCMPLT: "efdcmplt",
2429 EFDTSTGT: "efdtstgt",
2430 EFDTSTLT: "efdtstlt",
2431 EFDCFSI: "efdcfsi",
2432 EFDTSTEQ: "efdtsteq",
2433 EFDCFUI: "efdcfui",
2434 EFDCFSID: "efdcfsid",
2435 EFDCFSF: "efdcfsf",
2436 EFDCFUF: "efdcfuf",
2437 EFDCFUID: "efdcfuid",
2438 EFDCTSI: "efdctsi",
2439 EFDCTUI: "efdctui",
2440 EFDCTSIDZ: "efdctsidz",
2441 EFDCTUIDZ: "efdctuidz",
2442 EFDCTSIZ: "efdctsiz",
2443 EFDCTSF: "efdctsf",
2444 EFDCTUF: "efdctuf",
2445 EFDCTUIZ: "efdctuiz",
2446 EFDCFS: "efdcfs",
2447 EFSCFD: "efscfd",
2448 DLMZB: "dlmzb",
2449 DLMZBCC: "dlmzb.",
2450 MACCHW: "macchw",
2451 MACCHWCC: "macchw.",
2452 MACCHWO: "macchwo",
2453 MACCHWOCC: "macchwo.",
2454 MACCHWS: "macchws",
2455 MACCHWSCC: "macchws.",
2456 MACCHWSO: "macchwso",
2457 MACCHWSOCC: "macchwso.",
2458 MACCHWU: "macchwu",
2459 MACCHWUCC: "macchwu.",
2460 MACCHWUO: "macchwuo",
2461 MACCHWUOCC: "macchwuo.",
2462 MACCHWSU: "macchwsu",
2463 MACCHWSUCC: "macchwsu.",
2464 MACCHWSUO: "macchwsuo",
2465 MACCHWSUOCC: "macchwsuo.",
2466 MACHHW: "machhw",
2467 MACHHWCC: "machhw.",
2468 MACHHWO: "machhwo",
2469 MACHHWOCC: "machhwo.",
2470 MACHHWS: "machhws",
2471 MACHHWSCC: "machhws.",
2472 MACHHWSO: "machhwso",
2473 MACHHWSOCC: "machhwso.",
2474 MACHHWU: "machhwu",
2475 MACHHWUCC: "machhwu.",
2476 MACHHWUO: "machhwuo",
2477 MACHHWUOCC: "machhwuo.",
2478 MACHHWSU: "machhwsu",
2479 MACHHWSUCC: "machhwsu.",
2480 MACHHWSUO: "machhwsuo",
2481 MACHHWSUOCC: "machhwsuo.",
2482 MACLHW: "maclhw",
2483 MACLHWCC: "maclhw.",
2484 MACLHWO: "maclhwo",
2485 MACLHWOCC: "maclhwo.",
2486 MACLHWS: "maclhws",
2487 MACLHWSCC: "maclhws.",
2488 MACLHWSO: "maclhwso",
2489 MACLHWSOCC: "maclhwso.",
2490 MACLHWU: "maclhwu",
2491 MACLHWUCC: "maclhwu.",
2492 MACLHWUO: "maclhwuo",
2493 MACLHWUOCC: "maclhwuo.",
2494 MULCHW: "mulchw",
2495 MULCHWCC: "mulchw.",
2496 MACLHWSU: "maclhwsu",
2497 MACLHWSUCC: "maclhwsu.",
2498 MACLHWSUO: "maclhwsuo",
2499 MACLHWSUOCC: "maclhwsuo.",
2500 MULCHWU: "mulchwu",
2501 MULCHWUCC: "mulchwu.",
2502 MULHHW: "mulhhw",
2503 MULHHWCC: "mulhhw.",
2504 MULLHW: "mullhw",
2505 MULLHWCC: "mullhw.",
2506 MULHHWU: "mulhhwu",
2507 MULHHWUCC: "mulhhwu.",
2508 MULLHWU: "mullhwu",
2509 MULLHWUCC: "mullhwu.",
2510 NMACCHW: "nmacchw",
2511 NMACCHWCC: "nmacchw.",
2512 NMACCHWO: "nmacchwo",
2513 NMACCHWOCC: "nmacchwo.",
2514 NMACCHWS: "nmacchws",
2515 NMACCHWSCC: "nmacchws.",
2516 NMACCHWSO: "nmacchwso",
2517 NMACCHWSOCC: "nmacchwso.",
2518 NMACHHW: "nmachhw",
2519 NMACHHWCC: "nmachhw.",
2520 NMACHHWO: "nmachhwo",
2521 NMACHHWOCC: "nmachhwo.",
2522 NMACHHWS: "nmachhws",
2523 NMACHHWSCC: "nmachhws.",
2524 NMACHHWSO: "nmachhwso",
2525 NMACHHWSOCC: "nmachhwso.",
2526 NMACLHW: "nmaclhw",
2527 NMACLHWCC: "nmaclhw.",
2528 NMACLHWO: "nmaclhwo",
2529 NMACLHWOCC: "nmaclhwo.",
2530 NMACLHWS: "nmaclhws",
2531 NMACLHWSCC: "nmaclhws.",
2532 NMACLHWSO: "nmaclhwso",
2533 NMACLHWSOCC: "nmaclhwso.",
2534 ICBI: "icbi",
2535 ICBT: "icbt",
2536 DCBA: "dcba",
2537 DCBT: "dcbt",
2538 DCBTST: "dcbtst",
2539 DCBZ: "dcbz",
2540 DCBST: "dcbst",
2541 DCBF: "dcbf",
2542 ISYNC: "isync",
2543 LBARX: "lbarx",
2544 LHARX: "lharx",
2545 LWARX: "lwarx",
2546 STBCXCC: "stbcx.",
2547 STHCXCC: "sthcx.",
2548 STWCXCC: "stwcx.",
2549 LDARX: "ldarx",
2550 STDCXCC: "stdcx.",
2551 LQARX: "lqarx",
2552 STQCXCC: "stqcx.",
2553 SYNC: "sync",
2554 EIEIO: "eieio",
2555 MBAR: "mbar",
2556 WAIT: "wait",
2557 TBEGINCC: "tbegin.",
2558 TENDCC: "tend.",
2559 TABORTCC: "tabort.",
2560 TABORTWCCC: "tabortwc.",
2561 TABORTWCICC: "tabortwci.",
2562 TABORTDCCC: "tabortdc.",
2563 TABORTDCICC: "tabortdci.",
2564 TSRCC: "tsr.",
2565 TCHECK: "tcheck",
2566 MFTB: "mftb",
2567 RFEBB: "rfebb",
2568 LBDX: "lbdx",
2569 LHDX: "lhdx",
2570 LWDX: "lwdx",
2571 LDDX: "lddx",
2572 LFDDX: "lfddx",
2573 STBDX: "stbdx",
2574 STHDX: "sthdx",
2575 STWDX: "stwdx",
2576 STDDX: "stddx",
2577 STFDDX: "stfddx",
2578 DSN: "dsn",
2579 ECIWX: "eciwx",
2580 ECOWX: "ecowx",
2581 RFID: "rfid",
2582 HRFID: "hrfid",
2583 DOZE: "doze",
2584 NAP: "nap",
2585 SLEEP: "sleep",
2586 RVWINKLE: "rvwinkle",
2587 LBZCIX: "lbzcix",
2588 LWZCIX: "lwzcix",
2589 LHZCIX: "lhzcix",
2590 LDCIX: "ldcix",
2591 STBCIX: "stbcix",
2592 STWCIX: "stwcix",
2593 STHCIX: "sthcix",
2594 STDCIX: "stdcix",
2595 TRECLAIMCC: "treclaim.",
2596 TRECHKPTCC: "trechkpt.",
2597 MTMSR: "mtmsr",
2598 MTMSRD: "mtmsrd",
2599 MFMSR: "mfmsr",
2600 SLBIE: "slbie",
2601 SLBIA: "slbia",
2602 SLBMTE: "slbmte",
2603 SLBMFEV: "slbmfev",
2604 SLBMFEE: "slbmfee",
2605 SLBFEECC: "slbfee.",
2606 MTSR: "mtsr",
2607 MTSRIN: "mtsrin",
2608 MFSR: "mfsr",
2609 MFSRIN: "mfsrin",
2610 TLBIE: "tlbie",
2611 TLBIEL: "tlbiel",
2612 TLBIA: "tlbia",
2613 TLBSYNC: "tlbsync",
2614 MSGSND: "msgsnd",
2615 MSGCLR: "msgclr",
2616 MSGSNDP: "msgsndp",
2617 MSGCLRP: "msgclrp",
2618 MTTMR: "mttmr",
2619 RFI: "rfi",
2620 RFCI: "rfci",
2621 RFDI: "rfdi",
2622 RFMCI: "rfmci",
2623 RFGI: "rfgi",
2624 EHPRIV: "ehpriv",
2625 MTDCR: "mtdcr",
2626 MTDCRX: "mtdcrx",
2627 MFDCR: "mfdcr",
2628 MFDCRX: "mfdcrx",
2629 WRTEE: "wrtee",
2630 WRTEEI: "wrteei",
2631 LBEPX: "lbepx",
2632 LHEPX: "lhepx",
2633 LWEPX: "lwepx",
2634 LDEPX: "ldepx",
2635 STBEPX: "stbepx",
2636 STHEPX: "sthepx",
2637 STWEPX: "stwepx",
2638 STDEPX: "stdepx",
2639 DCBSTEP: "dcbstep",
2640 DCBTEP: "dcbtep",
2641 DCBFEP: "dcbfep",
2642 DCBTSTEP: "dcbtstep",
2643 ICBIEP: "icbiep",
2644 DCBZEP: "dcbzep",
2645 LFDEPX: "lfdepx",
2646 STFDEPX: "stfdepx",
2647 EVLDDEPX: "evlddepx",
2648 EVSTDDEPX: "evstddepx",
2649 LVEPX: "lvepx",
2650 LVEPXL: "lvepxl",
2651 STVEPX: "stvepx",
2652 STVEPXL: "stvepxl",
2653 DCBI: "dcbi",
2654 DCBLQCC: "dcblq.",
2655 ICBLQCC: "icblq.",
2656 DCBTLS: "dcbtls",
2657 DCBTSTLS: "dcbtstls",
2658 ICBTLS: "icbtls",
2659 ICBLC: "icblc",
2660 DCBLC: "dcblc",
2661 TLBIVAX: "tlbivax",
2662 TLBILX: "tlbilx",
2663 TLBSX: "tlbsx",
2664 TLBSRXCC: "tlbsrx.",
2665 TLBRE: "tlbre",
2666 TLBWE: "tlbwe",
2667 DNH: "dnh",
2668 DCI: "dci",
2669 ICI: "ici",
2670 DCREAD: "dcread",
2671 ICREAD: "icread",
2672 MFPMR: "mfpmr",
2673 MTPMR: "mtpmr",
2674 ADDEX: "addex",
2675 DARN: "darn",
2676 MADDHD: "maddhd",
2677 MADDHDU: "maddhdu",
2678 MADDLD: "maddld",
2679 CMPRB: "cmprb",
2680 CMPEQB: "cmpeqb",
2681 EXTSWSLI: "extswsli",
2682 EXTSWSLICC: "extswsli.",
2683 MFVSRLD: "mfvsrld",
2684 MTVSRDD: "mtvsrdd",
2685 MTVSRWS: "mtvsrws",
2686 MCRXRX: "mcrxrx",
2687 COPY: "copy",
2688 PASTECC: "paste.",
2689 }
2690
2691 var (
2692 ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}}
2693 ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}}
2694 ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}}
2695 ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}}
2696 ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}}
2697 ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}}
2698 ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}}
2699 ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}}
2700 ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}}
2701 ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}}
2702 ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}}
2703 ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}}
2704 ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}}
2705 ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}}
2706 ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}}
2707 ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}}
2708 ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}}
2709 ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}}
2710 ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}}
2711 ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}}
2712 ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}}
2713 ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}}
2714 ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}}
2715 ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}}
2716 ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}}
2717 ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
2718 ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}}
2719 ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}}
2720 ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}}
2721 ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}}
2722 ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}}
2723 ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}}
2724 ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}}
2725 ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}}
2726 ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}}
2727 ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}}
2728 ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}}
2729 ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}}
2730 ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}}
2731 ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}}
2732 ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}}
2733 ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}}
2734 ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}}
2735 ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}}
2736 ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}}
2737 ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}}
2738 ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}}
2739 ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}}
2740 ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}}
2741 ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}}
2742 ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}}
2743 ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}}
2744 ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}}
2745 ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}}
2746 ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}}
2747 ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}}
2748 ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}}
2749 ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}}
2750 ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}}
2751 ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}}
2752 ap_CondRegField_29_31 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}}
2753 ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}}
2754 ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}}
2755 ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}}
2756 ap_ImmSigned_16_20 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}}
2757 ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}}
2758 ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}}
2759 ap_SpReg_12_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}}
2760 ap_ImmUnsigned_6_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}}
2761 ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}}
2762 ap_Reg_21_25 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{21, 5}}}
2763 )
2764
2765 var instFormats = [...]instFormat{
2766 {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800,
2767 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
2768 {CNTLZWCC, 0xfc0007ff, 0x7c000035, 0xf800,
2769 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
2770 {B, 0xfc000003, 0x48000000, 0x0,
2771 [5]*argField{ap_PCRel_6_29_shift2}},
2772 {BA, 0xfc000003, 0x48000002, 0x0,
2773 [5]*argField{ap_Label_6_29_shift2}},
2774 {BL, 0xfc000003, 0x48000001, 0x0,
2775 [5]*argField{ap_PCRel_6_29_shift2}},
2776 {BLA, 0xfc000003, 0x48000003, 0x0,
2777 [5]*argField{ap_Label_6_29_shift2}},
2778 {BC, 0xfc000003, 0x40000000, 0x0,
2779 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
2780 {BCA, 0xfc000003, 0x40000002, 0x0,
2781 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
2782 {BCL, 0xfc000003, 0x40000001, 0x0,
2783 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}},
2784 {BCLA, 0xfc000003, 0x40000003, 0x0,
2785 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}},
2786 {BCLR, 0xfc0007ff, 0x4c000020, 0xe000,
2787 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2788 {BCLRL, 0xfc0007ff, 0x4c000021, 0xe000,
2789 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2790 {BCCTR, 0xfc0007ff, 0x4c000420, 0xe000,
2791 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2792 {BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000,
2793 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2794 {BCTAR, 0xfc0007ff, 0x4c000460, 0xe000,
2795 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2796 {BCTARL, 0xfc0007ff, 0x4c000461, 0xe000,
2797 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}},
2798 {CRAND, 0xfc0007fe, 0x4c000202, 0x1,
2799 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2800 {CROR, 0xfc0007fe, 0x4c000382, 0x1,
2801 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2802 {CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1,
2803 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2804 {CRXOR, 0xfc0007fe, 0x4c000182, 0x1,
2805 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2806 {CRNOR, 0xfc0007fe, 0x4c000042, 0x1,
2807 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2808 {CRANDC, 0xfc0007fe, 0x4c000102, 0x1,
2809 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2810 {MCRF, 0xfc0007fe, 0x4c000000, 0x63f801,
2811 [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
2812 {CREQV, 0xfc0007fe, 0x4c000242, 0x1,
2813 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2814 {CRORC, 0xfc0007fe, 0x4c000342, 0x1,
2815 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}},
2816 {SC, 0xfc000002, 0x44000002, 0x3fff01d,
2817 [5]*argField{ap_ImmUnsigned_20_26}},
2818 {CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801,
2819 [5]*argField{}},
2820 {MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1,
2821 [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
2822 {LBZ, 0xfc000000, 0x88000000, 0x0,
2823 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2824 {LBZU, 0xfc000000, 0x8c000000, 0x0,
2825 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2826 {LBZX, 0xfc0007fe, 0x7c0000ae, 0x1,
2827 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2828 {LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1,
2829 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2830 {LHZ, 0xfc000000, 0xa0000000, 0x0,
2831 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2832 {LHZU, 0xfc000000, 0xa4000000, 0x0,
2833 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2834 {LHZX, 0xfc0007fe, 0x7c00022e, 0x1,
2835 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2836 {LHZUX, 0xfc0007fe, 0x7c00026e, 0x1,
2837 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2838 {LHA, 0xfc000000, 0xa8000000, 0x0,
2839 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2840 {LHAU, 0xfc000000, 0xac000000, 0x0,
2841 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2842 {LHAX, 0xfc0007fe, 0x7c0002ae, 0x1,
2843 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2844 {LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1,
2845 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2846 {LWZ, 0xfc000000, 0x80000000, 0x0,
2847 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2848 {LWZU, 0xfc000000, 0x84000000, 0x0,
2849 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2850 {LWZX, 0xfc0007fe, 0x7c00002e, 0x1,
2851 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2852 {LWZUX, 0xfc0007fe, 0x7c00006e, 0x1,
2853 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2854 {LWA, 0xfc000003, 0xe8000002, 0x0,
2855 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2856 {LWAX, 0xfc0007fe, 0x7c0002aa, 0x1,
2857 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2858 {LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1,
2859 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2860 {LD, 0xfc000003, 0xe8000000, 0x0,
2861 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2862 {LDU, 0xfc000003, 0xe8000001, 0x0,
2863 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2864 {LDX, 0xfc0007fe, 0x7c00002a, 0x1,
2865 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2866 {LDUX, 0xfc0007fe, 0x7c00006a, 0x1,
2867 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2868 {STB, 0xfc000000, 0x98000000, 0x0,
2869 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2870 {STBU, 0xfc000000, 0x9c000000, 0x0,
2871 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2872 {STBX, 0xfc0007fe, 0x7c0001ae, 0x1,
2873 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2874 {STBUX, 0xfc0007fe, 0x7c0001ee, 0x1,
2875 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2876 {STH, 0xfc000000, 0xb0000000, 0x0,
2877 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2878 {STHU, 0xfc000000, 0xb4000000, 0x0,
2879 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2880 {STHX, 0xfc0007fe, 0x7c00032e, 0x1,
2881 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2882 {STHUX, 0xfc0007fe, 0x7c00036e, 0x1,
2883 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2884 {STW, 0xfc000000, 0x90000000, 0x0,
2885 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2886 {STWU, 0xfc000000, 0x94000000, 0x0,
2887 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2888 {STWX, 0xfc0007fe, 0x7c00012e, 0x1,
2889 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2890 {STWUX, 0xfc0007fe, 0x7c00016e, 0x1,
2891 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2892 {STD, 0xfc000003, 0xf8000000, 0x0,
2893 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2894 {STDU, 0xfc000003, 0xf8000001, 0x0,
2895 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2896 {STDX, 0xfc0007fe, 0x7c00012a, 0x1,
2897 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2898 {STDUX, 0xfc0007fe, 0x7c00016a, 0x1,
2899 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2900 {LQ, 0xfc000000, 0xe0000000, 0xf,
2901 [5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}},
2902 {STQ, 0xfc000003, 0xf8000002, 0x0,
2903 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
2904 {LHBRX, 0xfc0007fe, 0x7c00062c, 0x1,
2905 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2906 {LWBRX, 0xfc0007fe, 0x7c00042c, 0x1,
2907 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2908 {STHBRX, 0xfc0007fe, 0x7c00072c, 0x1,
2909 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2910 {STWBRX, 0xfc0007fe, 0x7c00052c, 0x1,
2911 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2912 {LDBRX, 0xfc0007fe, 0x7c000428, 0x1,
2913 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2914 {STDBRX, 0xfc0007fe, 0x7c000528, 0x1,
2915 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2916 {LMW, 0xfc000000, 0xb8000000, 0x0,
2917 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2918 {STMW, 0xfc000000, 0xbc000000, 0x0,
2919 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
2920 {LSWI, 0xfc0007fe, 0x7c0004aa, 0x1,
2921 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
2922 {LSWX, 0xfc0007fe, 0x7c00042a, 0x1,
2923 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2924 {STSWI, 0xfc0007fe, 0x7c0005aa, 0x1,
2925 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
2926 {STSWX, 0xfc0007fe, 0x7c00052a, 0x1,
2927 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2928 {LI, 0xfc1f0000, 0x38000000, 0x0,
2929 [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
2930 {ADDI, 0xfc000000, 0x38000000, 0x0,
2931 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
2932 {LIS, 0xfc1f0000, 0x3c000000, 0x0,
2933 [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}},
2934 {ADDIS, 0xfc000000, 0x3c000000, 0x0,
2935 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
2936 {ADD, 0xfc0007ff, 0x7c000214, 0x0,
2937 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2938 {ADDCC, 0xfc0007ff, 0x7c000215, 0x0,
2939 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2940 {ADDO, 0xfc0007ff, 0x7c000614, 0x0,
2941 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2942 {ADDOCC, 0xfc0007ff, 0x7c000615, 0x0,
2943 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2944 {ADDIC, 0xfc000000, 0x30000000, 0x0,
2945 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
2946 {SUBF, 0xfc0007ff, 0x7c000050, 0x0,
2947 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2948 {SUBFCC, 0xfc0007ff, 0x7c000051, 0x0,
2949 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2950 {SUBFO, 0xfc0007ff, 0x7c000450, 0x0,
2951 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2952 {SUBFOCC, 0xfc0007ff, 0x7c000451, 0x0,
2953 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2954 {ADDICCC, 0xfc000000, 0x34000000, 0x0,
2955 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
2956 {SUBFIC, 0xfc000000, 0x20000000, 0x0,
2957 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
2958 {ADDC, 0xfc0007ff, 0x7c000014, 0x0,
2959 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2960 {ADDCCC, 0xfc0007ff, 0x7c000015, 0x0,
2961 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2962 {ADDCO, 0xfc0007ff, 0x7c000414, 0x0,
2963 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2964 {ADDCOCC, 0xfc0007ff, 0x7c000415, 0x0,
2965 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2966 {SUBFC, 0xfc0007ff, 0x7c000010, 0x0,
2967 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2968 {SUBFCCC, 0xfc0007ff, 0x7c000011, 0x0,
2969 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2970 {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0,
2971 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2972 {SUBFCOCC, 0xfc0007ff, 0x7c000411, 0x0,
2973 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2974 {ADDE, 0xfc0007ff, 0x7c000114, 0x0,
2975 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2976 {ADDECC, 0xfc0007ff, 0x7c000115, 0x0,
2977 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2978 {ADDEO, 0xfc0007ff, 0x7c000514, 0x0,
2979 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2980 {ADDEOCC, 0xfc0007ff, 0x7c000515, 0x0,
2981 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2982 {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800,
2983 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
2984 {ADDMECC, 0xfc0007ff, 0x7c0001d5, 0xf800,
2985 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
2986 {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800,
2987 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
2988 {ADDMEOCC, 0xfc0007ff, 0x7c0005d5, 0xf800,
2989 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
2990 {SUBFE, 0xfc0007ff, 0x7c000110, 0x0,
2991 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2992 {SUBFECC, 0xfc0007ff, 0x7c000111, 0x0,
2993 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2994 {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0,
2995 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2996 {SUBFEOCC, 0xfc0007ff, 0x7c000511, 0x0,
2997 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
2998 {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800,
2999 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3000 {SUBFMECC, 0xfc0007ff, 0x7c0001d1, 0xf800,
3001 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3002 {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800,
3003 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3004 {SUBFMEOCC, 0xfc0007ff, 0x7c0005d1, 0xf800,
3005 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3006 {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800,
3007 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3008 {ADDZECC, 0xfc0007ff, 0x7c000195, 0xf800,
3009 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3010 {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800,
3011 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3012 {ADDZEOCC, 0xfc0007ff, 0x7c000595, 0xf800,
3013 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3014 {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800,
3015 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3016 {SUBFZECC, 0xfc0007ff, 0x7c000191, 0xf800,
3017 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3018 {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800,
3019 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3020 {SUBFZEOCC, 0xfc0007ff, 0x7c000591, 0xf800,
3021 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3022 {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800,
3023 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3024 {NEGCC, 0xfc0007ff, 0x7c0000d1, 0xf800,
3025 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3026 {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800,
3027 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3028 {NEGOCC, 0xfc0007ff, 0x7c0004d1, 0xf800,
3029 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3030 {MULLI, 0xfc000000, 0x1c000000, 0x0,
3031 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
3032 {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0,
3033 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3034 {MULLWCC, 0xfc0007ff, 0x7c0001d7, 0x0,
3035 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3036 {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0,
3037 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3038 {MULLWOCC, 0xfc0007ff, 0x7c0005d7, 0x0,
3039 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3040 {MULHW, 0xfc0003ff, 0x7c000096, 0x400,
3041 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3042 {MULHWCC, 0xfc0003ff, 0x7c000097, 0x400,
3043 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3044 {MULHWU, 0xfc0003ff, 0x7c000016, 0x400,
3045 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3046 {MULHWUCC, 0xfc0003ff, 0x7c000017, 0x400,
3047 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3048 {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0,
3049 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3050 {DIVWCC, 0xfc0007ff, 0x7c0003d7, 0x0,
3051 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3052 {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0,
3053 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3054 {DIVWOCC, 0xfc0007ff, 0x7c0007d7, 0x0,
3055 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3056 {DIVWU, 0xfc0007ff, 0x7c000396, 0x0,
3057 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3058 {DIVWUCC, 0xfc0007ff, 0x7c000397, 0x0,
3059 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3060 {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0,
3061 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3062 {DIVWUOCC, 0xfc0007ff, 0x7c000797, 0x0,
3063 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3064 {DIVWE, 0xfc0007ff, 0x7c000356, 0x0,
3065 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3066 {DIVWECC, 0xfc0007ff, 0x7c000357, 0x0,
3067 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3068 {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0,
3069 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3070 {DIVWEOCC, 0xfc0007ff, 0x7c000757, 0x0,
3071 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3072 {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0,
3073 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3074 {DIVWEUCC, 0xfc0007ff, 0x7c000317, 0x0,
3075 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3076 {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0,
3077 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3078 {DIVWEUOCC, 0xfc0007ff, 0x7c000717, 0x0,
3079 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3080 {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0,
3081 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3082 {MULLDCC, 0xfc0007ff, 0x7c0001d3, 0x0,
3083 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3084 {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0,
3085 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3086 {MULLDOCC, 0xfc0007ff, 0x7c0005d3, 0x0,
3087 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3088 {MULHDU, 0xfc0003ff, 0x7c000012, 0x400,
3089 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3090 {MULHDUCC, 0xfc0003ff, 0x7c000013, 0x400,
3091 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3092 {MULHD, 0xfc0003ff, 0x7c000092, 0x400,
3093 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3094 {MULHDCC, 0xfc0003ff, 0x7c000093, 0x400,
3095 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3096 {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0,
3097 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3098 {DIVDCC, 0xfc0007ff, 0x7c0003d3, 0x0,
3099 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3100 {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0,
3101 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3102 {DIVDOCC, 0xfc0007ff, 0x7c0007d3, 0x0,
3103 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3104 {DIVDU, 0xfc0007ff, 0x7c000392, 0x0,
3105 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3106 {DIVDUCC, 0xfc0007ff, 0x7c000393, 0x0,
3107 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3108 {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0,
3109 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3110 {DIVDUOCC, 0xfc0007ff, 0x7c000793, 0x0,
3111 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3112 {DIVDE, 0xfc0007ff, 0x7c000352, 0x0,
3113 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3114 {DIVDECC, 0xfc0007ff, 0x7c000353, 0x0,
3115 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3116 {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0,
3117 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3118 {DIVDEOCC, 0xfc0007ff, 0x7c000753, 0x0,
3119 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3120 {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0,
3121 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3122 {DIVDEUCC, 0xfc0007ff, 0x7c000313, 0x0,
3123 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3124 {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0,
3125 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3126 {DIVDEUOCC, 0xfc0007ff, 0x7c000713, 0x0,
3127 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3128 {CMPWI, 0xfc200000, 0x2c000000, 0x400000,
3129 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
3130 {CMPDI, 0xfc200000, 0x2c200000, 0x400000,
3131 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}},
3132 {CMPW, 0xfc2007fe, 0x7c000000, 0x400001,
3133 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
3134 {CMPD, 0xfc2007fe, 0x7c200000, 0x400001,
3135 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
3136 {CMPLWI, 0xfc200000, 0x28000000, 0x400000,
3137 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
3138 {CMPLDI, 0xfc200000, 0x28200000, 0x400000,
3139 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}},
3140 {CMPLW, 0xfc2007fe, 0x7c000040, 0x400001,
3141 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
3142 {CMPLD, 0xfc2007fe, 0x7c200040, 0x400001,
3143 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
3144 {TWI, 0xfc000000, 0xc000000, 0x0,
3145 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
3146 {TW, 0xfc0007fe, 0x7c000008, 0x1,
3147 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3148 {TDI, 0xfc000000, 0x8000000, 0x0,
3149 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}},
3150 {ISEL, 0xfc00003e, 0x7c00001e, 0x1,
3151 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}},
3152 {TD, 0xfc0007fe, 0x7c000088, 0x1,
3153 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3154 {ANDICC, 0xfc000000, 0x70000000, 0x0,
3155 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3156 {ANDISCC, 0xfc000000, 0x74000000, 0x0,
3157 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3158 {ORI, 0xfc000000, 0x60000000, 0x0,
3159 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3160 {ORIS, 0xfc000000, 0x64000000, 0x0,
3161 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3162 {XORI, 0xfc000000, 0x68000000, 0x0,
3163 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3164 {XORIS, 0xfc000000, 0x6c000000, 0x0,
3165 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}},
3166 {AND, 0xfc0007ff, 0x7c000038, 0x0,
3167 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3168 {ANDCC, 0xfc0007ff, 0x7c000039, 0x0,
3169 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3170 {XOR, 0xfc0007ff, 0x7c000278, 0x0,
3171 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3172 {XORCC, 0xfc0007ff, 0x7c000279, 0x0,
3173 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3174 {NAND, 0xfc0007ff, 0x7c0003b8, 0x0,
3175 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3176 {NANDCC, 0xfc0007ff, 0x7c0003b9, 0x0,
3177 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3178 {OR, 0xfc0007ff, 0x7c000378, 0x0,
3179 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3180 {ORCC, 0xfc0007ff, 0x7c000379, 0x0,
3181 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3182 {NOR, 0xfc0007ff, 0x7c0000f8, 0x0,
3183 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3184 {NORCC, 0xfc0007ff, 0x7c0000f9, 0x0,
3185 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3186 {ANDC, 0xfc0007ff, 0x7c000078, 0x0,
3187 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3188 {ANDCCC, 0xfc0007ff, 0x7c000079, 0x0,
3189 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3190 {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800,
3191 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3192 {EXTSBCC, 0xfc0007ff, 0x7c000775, 0xf800,
3193 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3194 {EQV, 0xfc0007ff, 0x7c000238, 0x0,
3195 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3196 {EQVCC, 0xfc0007ff, 0x7c000239, 0x0,
3197 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3198 {ORC, 0xfc0007ff, 0x7c000338, 0x0,
3199 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3200 {ORCCC, 0xfc0007ff, 0x7c000339, 0x0,
3201 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3202 {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800,
3203 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3204 {EXTSHCC, 0xfc0007ff, 0x7c000735, 0xf800,
3205 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3206 {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1,
3207 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3208 {POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801,
3209 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3210 {POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801,
3211 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3212 {PRTYD, 0xfc0007fe, 0x7c000174, 0xf801,
3213 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3214 {PRTYW, 0xfc0007fe, 0x7c000134, 0xf801,
3215 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3216 {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800,
3217 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3218 {EXTSWCC, 0xfc0007ff, 0x7c0007b5, 0xf800,
3219 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3220 {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800,
3221 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3222 {CNTLZDCC, 0xfc0007ff, 0x7c000075, 0xf800,
3223 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3224 {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801,
3225 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3226 {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1,
3227 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3228 {RLWINM, 0xfc000001, 0x54000000, 0x0,
3229 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3230 {RLWINMCC, 0xfc000001, 0x54000001, 0x0,
3231 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3232 {RLWNM, 0xfc000001, 0x5c000000, 0x0,
3233 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3234 {RLWNMCC, 0xfc000001, 0x5c000001, 0x0,
3235 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3236 {RLWIMI, 0xfc000001, 0x50000000, 0x0,
3237 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3238 {RLWIMICC, 0xfc000001, 0x50000001, 0x0,
3239 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}},
3240 {RLDICL, 0xfc00001d, 0x78000000, 0x0,
3241 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3242 {RLDICLCC, 0xfc00001d, 0x78000001, 0x0,
3243 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3244 {RLDICR, 0xfc00001d, 0x78000004, 0x0,
3245 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3246 {RLDICRCC, 0xfc00001d, 0x78000005, 0x0,
3247 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3248 {RLDIC, 0xfc00001d, 0x78000008, 0x0,
3249 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3250 {RLDICCC, 0xfc00001d, 0x78000009, 0x0,
3251 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3252 {RLDCL, 0xfc00001f, 0x78000010, 0x0,
3253 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
3254 {RLDCLCC, 0xfc00001f, 0x78000011, 0x0,
3255 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
3256 {RLDCR, 0xfc00001f, 0x78000012, 0x0,
3257 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
3258 {RLDCRCC, 0xfc00001f, 0x78000013, 0x0,
3259 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}},
3260 {RLDIMI, 0xfc00001d, 0x7800000c, 0x0,
3261 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3262 {RLDIMICC, 0xfc00001d, 0x7800000d, 0x0,
3263 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}},
3264 {SLW, 0xfc0007ff, 0x7c000030, 0x0,
3265 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3266 {SLWCC, 0xfc0007ff, 0x7c000031, 0x0,
3267 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3268 {SRW, 0xfc0007ff, 0x7c000430, 0x0,
3269 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3270 {SRWCC, 0xfc0007ff, 0x7c000431, 0x0,
3271 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3272 {SRAWI, 0xfc0007ff, 0x7c000670, 0x0,
3273 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
3274 {SRAWICC, 0xfc0007ff, 0x7c000671, 0x0,
3275 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}},
3276 {SRAW, 0xfc0007ff, 0x7c000630, 0x0,
3277 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3278 {SRAWCC, 0xfc0007ff, 0x7c000631, 0x0,
3279 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3280 {SLD, 0xfc0007ff, 0x7c000036, 0x0,
3281 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3282 {SLDCC, 0xfc0007ff, 0x7c000037, 0x0,
3283 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3284 {SRD, 0xfc0007ff, 0x7c000436, 0x0,
3285 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3286 {SRDCC, 0xfc0007ff, 0x7c000437, 0x0,
3287 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3288 {SRADI, 0xfc0007fd, 0x7c000674, 0x0,
3289 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
3290 {SRADICC, 0xfc0007fd, 0x7c000675, 0x0,
3291 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
3292 {SRAD, 0xfc0007ff, 0x7c000634, 0x0,
3293 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3294 {SRADCC, 0xfc0007ff, 0x7c000635, 0x0,
3295 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
3296 {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801,
3297 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3298 {CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801,
3299 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
3300 {ADDG6S, 0xfc0003fe, 0x7c000094, 0x401,
3301 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3302 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1,
3303 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
3304 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1,
3305 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
3306 {MTCRF, 0xfc1007fe, 0x7c000120, 0x801,
3307 [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
3308 {MFCR, 0xfc1007fe, 0x7c000026, 0xff801,
3309 [5]*argField{ap_Reg_6_10}},
3310 {MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801,
3311 [5]*argField{ap_ImmUnsigned_10_10}},
3312 {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800,
3313 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
3314 {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800,
3315 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
3316 {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800,
3317 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
3318 {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800,
3319 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
3320 {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800,
3321 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
3322 {MTOCRF, 0xfc1007fe, 0x7c100120, 0x801,
3323 [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}},
3324 {MFOCRF, 0xfc1007fe, 0x7c100026, 0x801,
3325 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}},
3326 {MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801,
3327 [5]*argField{ap_CondRegField_6_8}},
3328 {MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801,
3329 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3330 {MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801,
3331 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
3332 {LFS, 0xfc000000, 0xc0000000, 0x0,
3333 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3334 {LFSU, 0xfc000000, 0xc4000000, 0x0,
3335 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3336 {LFSX, 0xfc0007fe, 0x7c00042e, 0x1,
3337 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3338 {LFSUX, 0xfc0007fe, 0x7c00046e, 0x1,
3339 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3340 {LFD, 0xfc000000, 0xc8000000, 0x0,
3341 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3342 {LFDU, 0xfc000000, 0xcc000000, 0x0,
3343 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3344 {LFDX, 0xfc0007fe, 0x7c0004ae, 0x1,
3345 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3346 {LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1,
3347 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3348 {LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1,
3349 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3350 {LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1,
3351 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3352 {STFS, 0xfc000000, 0xd0000000, 0x0,
3353 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3354 {STFSU, 0xfc000000, 0xd4000000, 0x0,
3355 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3356 {STFSX, 0xfc0007fe, 0x7c00052e, 0x1,
3357 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3358 {STFSUX, 0xfc0007fe, 0x7c00056e, 0x1,
3359 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3360 {STFD, 0xfc000000, 0xd8000000, 0x0,
3361 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3362 {STFDU, 0xfc000000, 0xdc000000, 0x0,
3363 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}},
3364 {STFDX, 0xfc0007fe, 0x7c0005ae, 0x1,
3365 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3366 {STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1,
3367 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3368 {STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1,
3369 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3370 {LFDP, 0xfc000003, 0xe4000000, 0x0,
3371 [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
3372 {LFDPX, 0xfc0007fe, 0x7c00062e, 0x1,
3373 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3374 {STFDP, 0xfc000003, 0xf4000000, 0x0,
3375 [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}},
3376 {STFDPX, 0xfc0007fe, 0x7c00072e, 0x1,
3377 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3378 {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000,
3379 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3380 {FMRCC, 0xfc0007ff, 0xfc000091, 0x1f0000,
3381 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3382 {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000,
3383 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3384 {FABSCC, 0xfc0007ff, 0xfc000211, 0x1f0000,
3385 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3386 {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000,
3387 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3388 {FNABSCC, 0xfc0007ff, 0xfc000111, 0x1f0000,
3389 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3390 {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000,
3391 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3392 {FNEGCC, 0xfc0007ff, 0xfc000051, 0x1f0000,
3393 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3394 {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0,
3395 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3396 {FCPSGNCC, 0xfc0007ff, 0xfc000011, 0x0,
3397 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3398 {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1,
3399 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3400 {FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1,
3401 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3402 {FADD, 0xfc00003f, 0xfc00002a, 0x7c0,
3403 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3404 {FADDCC, 0xfc00003f, 0xfc00002b, 0x7c0,
3405 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3406 {FADDS, 0xfc00003f, 0xec00002a, 0x7c0,
3407 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3408 {FADDSCC, 0xfc00003f, 0xec00002b, 0x7c0,
3409 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3410 {FSUB, 0xfc00003f, 0xfc000028, 0x7c0,
3411 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3412 {FSUBCC, 0xfc00003f, 0xfc000029, 0x7c0,
3413 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3414 {FSUBS, 0xfc00003f, 0xec000028, 0x7c0,
3415 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3416 {FSUBSCC, 0xfc00003f, 0xec000029, 0x7c0,
3417 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3418 {FMUL, 0xfc00003f, 0xfc000032, 0xf800,
3419 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
3420 {FMULCC, 0xfc00003f, 0xfc000033, 0xf800,
3421 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
3422 {FMULS, 0xfc00003f, 0xec000032, 0xf800,
3423 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
3424 {FMULSCC, 0xfc00003f, 0xec000033, 0xf800,
3425 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}},
3426 {FDIV, 0xfc00003f, 0xfc000024, 0x7c0,
3427 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3428 {FDIVCC, 0xfc00003f, 0xfc000025, 0x7c0,
3429 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3430 {FDIVS, 0xfc00003f, 0xec000024, 0x7c0,
3431 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3432 {FDIVSCC, 0xfc00003f, 0xec000025, 0x7c0,
3433 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
3434 {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0,
3435 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3436 {FSQRTCC, 0xfc00003f, 0xfc00002d, 0x1f07c0,
3437 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3438 {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0,
3439 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3440 {FSQRTSCC, 0xfc00003f, 0xec00002d, 0x1f07c0,
3441 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3442 {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0,
3443 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3444 {FRECC, 0xfc00003f, 0xfc000031, 0x1f07c0,
3445 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3446 {FRES, 0xfc00003f, 0xec000030, 0x1f07c0,
3447 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3448 {FRESCC, 0xfc00003f, 0xec000031, 0x1f07c0,
3449 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3450 {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0,
3451 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3452 {FRSQRTECC, 0xfc00003f, 0xfc000035, 0x1f07c0,
3453 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3454 {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0,
3455 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3456 {FRSQRTESCC, 0xfc00003f, 0xec000035, 0x1f07c0,
3457 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3458 {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001,
3459 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
3460 {FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001,
3461 [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}},
3462 {FMADD, 0xfc00003f, 0xfc00003a, 0x0,
3463 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3464 {FMADDCC, 0xfc00003f, 0xfc00003b, 0x0,
3465 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3466 {FMADDS, 0xfc00003f, 0xec00003a, 0x0,
3467 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3468 {FMADDSCC, 0xfc00003f, 0xec00003b, 0x0,
3469 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3470 {FMSUB, 0xfc00003f, 0xfc000038, 0x0,
3471 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3472 {FMSUBCC, 0xfc00003f, 0xfc000039, 0x0,
3473 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3474 {FMSUBS, 0xfc00003f, 0xec000038, 0x0,
3475 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3476 {FMSUBSCC, 0xfc00003f, 0xec000039, 0x0,
3477 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3478 {FNMADD, 0xfc00003f, 0xfc00003e, 0x0,
3479 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3480 {FNMADDCC, 0xfc00003f, 0xfc00003f, 0x0,
3481 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3482 {FNMADDS, 0xfc00003f, 0xec00003e, 0x0,
3483 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3484 {FNMADDSCC, 0xfc00003f, 0xec00003f, 0x0,
3485 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3486 {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0,
3487 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3488 {FNMSUBCC, 0xfc00003f, 0xfc00003d, 0x0,
3489 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3490 {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0,
3491 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3492 {FNMSUBSCC, 0xfc00003f, 0xec00003d, 0x0,
3493 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3494 {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000,
3495 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3496 {FRSPCC, 0xfc0007ff, 0xfc000019, 0x1f0000,
3497 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3498 {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000,
3499 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3500 {FCTIDCC, 0xfc0007ff, 0xfc00065d, 0x1f0000,
3501 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3502 {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000,
3503 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3504 {FCTIDZCC, 0xfc0007ff, 0xfc00065f, 0x1f0000,
3505 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3506 {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000,
3507 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3508 {FCTIDUCC, 0xfc0007ff, 0xfc00075d, 0x1f0000,
3509 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3510 {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000,
3511 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3512 {FCTIDUZCC, 0xfc0007ff, 0xfc00075f, 0x1f0000,
3513 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3514 {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000,
3515 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3516 {FCTIWCC, 0xfc0007ff, 0xfc00001d, 0x1f0000,
3517 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3518 {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000,
3519 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3520 {FCTIWZCC, 0xfc0007ff, 0xfc00001f, 0x1f0000,
3521 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3522 {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000,
3523 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3524 {FCTIWUCC, 0xfc0007ff, 0xfc00011d, 0x1f0000,
3525 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3526 {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000,
3527 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3528 {FCTIWUZCC, 0xfc0007ff, 0xfc00011f, 0x1f0000,
3529 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3530 {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000,
3531 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3532 {FCFIDCC, 0xfc0007ff, 0xfc00069d, 0x1f0000,
3533 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3534 {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000,
3535 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3536 {FCFIDUCC, 0xfc0007ff, 0xfc00079d, 0x1f0000,
3537 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3538 {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000,
3539 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3540 {FCFIDSCC, 0xfc0007ff, 0xec00069d, 0x1f0000,
3541 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3542 {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000,
3543 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3544 {FCFIDUSCC, 0xfc0007ff, 0xec00079d, 0x1f0000,
3545 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3546 {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000,
3547 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3548 {FRINCC, 0xfc0007ff, 0xfc000311, 0x1f0000,
3549 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3550 {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000,
3551 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3552 {FRIZCC, 0xfc0007ff, 0xfc000351, 0x1f0000,
3553 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3554 {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000,
3555 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3556 {FRIPCC, 0xfc0007ff, 0xfc000391, 0x1f0000,
3557 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3558 {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000,
3559 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3560 {FRIMCC, 0xfc0007ff, 0xfc0003d1, 0x1f0000,
3561 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
3562 {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001,
3563 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
3564 {FCMPO, 0xfc0007fe, 0xfc000040, 0x600001,
3565 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
3566 {FSEL, 0xfc00003f, 0xfc00002e, 0x0,
3567 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3568 {FSELCC, 0xfc00003f, 0xfc00002f, 0x0,
3569 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}},
3570 {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800,
3571 [5]*argField{ap_FPReg_6_10}},
3572 {MFFSCC, 0xfc0007ff, 0xfc00048f, 0x1ff800,
3573 [5]*argField{ap_FPReg_6_10}},
3574 {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801,
3575 [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}},
3576 {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800,
3577 [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
3578 {MTFSFICC, 0xfc0007ff, 0xfc00010d, 0x7e0800,
3579 [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}},
3580 {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0,
3581 [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
3582 {MTFSFCC, 0xfc0007ff, 0xfc00058f, 0x0,
3583 [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}},
3584 {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800,
3585 [5]*argField{ap_CondRegBit_6_10}},
3586 {MTFSB0CC, 0xfc0007ff, 0xfc00008d, 0x1ff800,
3587 [5]*argField{ap_CondRegBit_6_10}},
3588 {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800,
3589 [5]*argField{ap_CondRegBit_6_10}},
3590 {MTFSB1CC, 0xfc0007ff, 0xfc00004d, 0x1ff800,
3591 [5]*argField{ap_CondRegBit_6_10}},
3592 {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1,
3593 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3594 {LVEHX, 0xfc0007fe, 0x7c00004e, 0x1,
3595 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3596 {LVEWX, 0xfc0007fe, 0x7c00008e, 0x1,
3597 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3598 {LVX, 0xfc0007fe, 0x7c0000ce, 0x1,
3599 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3600 {LVXL, 0xfc0007fe, 0x7c0002ce, 0x1,
3601 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3602 {STVEBX, 0xfc0007fe, 0x7c00010e, 0x1,
3603 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3604 {STVEHX, 0xfc0007fe, 0x7c00014e, 0x1,
3605 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3606 {STVEWX, 0xfc0007fe, 0x7c00018e, 0x1,
3607 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3608 {STVX, 0xfc0007fe, 0x7c0001ce, 0x1,
3609 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3610 {STVXL, 0xfc0007fe, 0x7c0003ce, 0x1,
3611 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3612 {LVSL, 0xfc0007fe, 0x7c00000c, 0x1,
3613 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3614 {LVSR, 0xfc0007fe, 0x7c00004c, 0x1,
3615 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
3616 {VPKPX, 0xfc0007ff, 0x1000030e, 0x0,
3617 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3618 {VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0,
3619 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3620 {VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0,
3621 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3622 {VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0,
3623 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3624 {VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0,
3625 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3626 {VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0,
3627 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3628 {VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0,
3629 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3630 {VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0,
3631 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3632 {VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0,
3633 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3634 {VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0,
3635 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3636 {VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0,
3637 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3638 {VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0,
3639 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3640 {VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0,
3641 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3642 {VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000,
3643 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3644 {VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000,
3645 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3646 {VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000,
3647 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3648 {VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000,
3649 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3650 {VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000,
3651 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3652 {VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000,
3653 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3654 {VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000,
3655 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3656 {VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000,
3657 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3658 {VMRGHB, 0xfc0007ff, 0x1000000c, 0x0,
3659 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3660 {VMRGHH, 0xfc0007ff, 0x1000004c, 0x0,
3661 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3662 {VMRGLB, 0xfc0007ff, 0x1000010c, 0x0,
3663 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3664 {VMRGLH, 0xfc0007ff, 0x1000014c, 0x0,
3665 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3666 {VMRGHW, 0xfc0007ff, 0x1000008c, 0x0,
3667 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3668 {VMRGLW, 0xfc0007ff, 0x1000018c, 0x0,
3669 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3670 {VMRGEW, 0xfc0007ff, 0x1000078c, 0x0,
3671 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3672 {VMRGOW, 0xfc0007ff, 0x1000068c, 0x0,
3673 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3674 {VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000,
3675 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}},
3676 {VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000,
3677 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}},
3678 {VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000,
3679 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}},
3680 {VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800,
3681 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
3682 {VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800,
3683 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
3684 {VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800,
3685 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}},
3686 {VPERM, 0xfc00003f, 0x1000002b, 0x0,
3687 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3688 {VSEL, 0xfc00003f, 0x1000002a, 0x0,
3689 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3690 {VSL, 0xfc0007ff, 0x100001c4, 0x0,
3691 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3692 {VSLDOI, 0xfc00003f, 0x1000002c, 0x400,
3693 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}},
3694 {VSLO, 0xfc0007ff, 0x1000040c, 0x0,
3695 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3696 {VSR, 0xfc0007ff, 0x100002c4, 0x0,
3697 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3698 {VSRO, 0xfc0007ff, 0x1000044c, 0x0,
3699 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3700 {VADDCUW, 0xfc0007ff, 0x10000180, 0x0,
3701 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3702 {VADDSBS, 0xfc0007ff, 0x10000300, 0x0,
3703 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3704 {VADDSHS, 0xfc0007ff, 0x10000340, 0x0,
3705 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3706 {VADDSWS, 0xfc0007ff, 0x10000380, 0x0,
3707 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3708 {VADDUBM, 0xfc0007ff, 0x10000000, 0x0,
3709 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3710 {VADDUDM, 0xfc0007ff, 0x100000c0, 0x0,
3711 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3712 {VADDUHM, 0xfc0007ff, 0x10000040, 0x0,
3713 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3714 {VADDUWM, 0xfc0007ff, 0x10000080, 0x0,
3715 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3716 {VADDUBS, 0xfc0007ff, 0x10000200, 0x0,
3717 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3718 {VADDUHS, 0xfc0007ff, 0x10000240, 0x0,
3719 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3720 {VADDUWS, 0xfc0007ff, 0x10000280, 0x0,
3721 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3722 {VADDUQM, 0xfc0007ff, 0x10000100, 0x0,
3723 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3724 {VADDEUQM, 0xfc00003f, 0x1000003c, 0x0,
3725 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3726 {VADDCUQ, 0xfc0007ff, 0x10000140, 0x0,
3727 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3728 {VADDECUQ, 0xfc00003f, 0x1000003d, 0x0,
3729 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3730 {VSUBCUW, 0xfc0007ff, 0x10000580, 0x0,
3731 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3732 {VSUBSBS, 0xfc0007ff, 0x10000700, 0x0,
3733 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3734 {VSUBSHS, 0xfc0007ff, 0x10000740, 0x0,
3735 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3736 {VSUBSWS, 0xfc0007ff, 0x10000780, 0x0,
3737 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3738 {VSUBUBM, 0xfc0007ff, 0x10000400, 0x0,
3739 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3740 {VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0,
3741 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3742 {VSUBUHM, 0xfc0007ff, 0x10000440, 0x0,
3743 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3744 {VSUBUWM, 0xfc0007ff, 0x10000480, 0x0,
3745 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3746 {VSUBUBS, 0xfc0007ff, 0x10000600, 0x0,
3747 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3748 {VSUBUHS, 0xfc0007ff, 0x10000640, 0x0,
3749 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3750 {VSUBUWS, 0xfc0007ff, 0x10000680, 0x0,
3751 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3752 {VSUBUQM, 0xfc0007ff, 0x10000500, 0x0,
3753 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3754 {VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0,
3755 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3756 {VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0,
3757 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3758 {VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0,
3759 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3760 {VMULESB, 0xfc0007ff, 0x10000308, 0x0,
3761 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3762 {VMULEUB, 0xfc0007ff, 0x10000208, 0x0,
3763 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3764 {VMULOSB, 0xfc0007ff, 0x10000108, 0x0,
3765 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3766 {VMULOUB, 0xfc0007ff, 0x10000008, 0x0,
3767 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3768 {VMULESH, 0xfc0007ff, 0x10000348, 0x0,
3769 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3770 {VMULEUH, 0xfc0007ff, 0x10000248, 0x0,
3771 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3772 {VMULOSH, 0xfc0007ff, 0x10000148, 0x0,
3773 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3774 {VMULOUH, 0xfc0007ff, 0x10000048, 0x0,
3775 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3776 {VMULESW, 0xfc0007ff, 0x10000388, 0x0,
3777 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3778 {VMULEUW, 0xfc0007ff, 0x10000288, 0x0,
3779 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3780 {VMULOSW, 0xfc0007ff, 0x10000188, 0x0,
3781 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3782 {VMULOUW, 0xfc0007ff, 0x10000088, 0x0,
3783 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3784 {VMULUWM, 0xfc0007ff, 0x10000089, 0x0,
3785 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3786 {VMHADDSHS, 0xfc00003f, 0x10000020, 0x0,
3787 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3788 {VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0,
3789 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3790 {VMLADDUHM, 0xfc00003f, 0x10000022, 0x0,
3791 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3792 {VMSUMUBM, 0xfc00003f, 0x10000024, 0x0,
3793 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3794 {VMSUMMBM, 0xfc00003f, 0x10000025, 0x0,
3795 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3796 {VMSUMSHM, 0xfc00003f, 0x10000028, 0x0,
3797 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3798 {VMSUMSHS, 0xfc00003f, 0x10000029, 0x0,
3799 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3800 {VMSUMUHM, 0xfc00003f, 0x10000026, 0x0,
3801 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3802 {VMSUMUHS, 0xfc00003f, 0x10000027, 0x0,
3803 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
3804 {VSUMSWS, 0xfc0007ff, 0x10000788, 0x0,
3805 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3806 {VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0,
3807 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3808 {VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0,
3809 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3810 {VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0,
3811 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3812 {VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0,
3813 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3814 {VAVGSB, 0xfc0007ff, 0x10000502, 0x0,
3815 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3816 {VAVGSH, 0xfc0007ff, 0x10000542, 0x0,
3817 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3818 {VAVGSW, 0xfc0007ff, 0x10000582, 0x0,
3819 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3820 {VAVGUB, 0xfc0007ff, 0x10000402, 0x0,
3821 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3822 {VAVGUW, 0xfc0007ff, 0x10000482, 0x0,
3823 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3824 {VAVGUH, 0xfc0007ff, 0x10000442, 0x0,
3825 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3826 {VMAXSB, 0xfc0007ff, 0x10000102, 0x0,
3827 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3828 {VMAXSD, 0xfc0007ff, 0x100001c2, 0x0,
3829 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3830 {VMAXUB, 0xfc0007ff, 0x10000002, 0x0,
3831 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3832 {VMAXUD, 0xfc0007ff, 0x100000c2, 0x0,
3833 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3834 {VMAXSH, 0xfc0007ff, 0x10000142, 0x0,
3835 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3836 {VMAXSW, 0xfc0007ff, 0x10000182, 0x0,
3837 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3838 {VMAXUH, 0xfc0007ff, 0x10000042, 0x0,
3839 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3840 {VMAXUW, 0xfc0007ff, 0x10000082, 0x0,
3841 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3842 {VMINSB, 0xfc0007ff, 0x10000302, 0x0,
3843 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3844 {VMINSD, 0xfc0007ff, 0x100003c2, 0x0,
3845 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3846 {VMINUB, 0xfc0007ff, 0x10000202, 0x0,
3847 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3848 {VMINUD, 0xfc0007ff, 0x100002c2, 0x0,
3849 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3850 {VMINSH, 0xfc0007ff, 0x10000342, 0x0,
3851 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3852 {VMINSW, 0xfc0007ff, 0x10000382, 0x0,
3853 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3854 {VMINUH, 0xfc0007ff, 0x10000242, 0x0,
3855 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3856 {VMINUW, 0xfc0007ff, 0x10000282, 0x0,
3857 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3858 {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0,
3859 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3860 {VCMPEQUBCC, 0xfc0007ff, 0x10000406, 0x0,
3861 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3862 {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0,
3863 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3864 {VCMPEQUHCC, 0xfc0007ff, 0x10000446, 0x0,
3865 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3866 {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0,
3867 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3868 {VCMPEQUWCC, 0xfc0007ff, 0x10000486, 0x0,
3869 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3870 {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0,
3871 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3872 {VCMPEQUDCC, 0xfc0007ff, 0x100004c7, 0x0,
3873 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3874 {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0,
3875 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3876 {VCMPGTSBCC, 0xfc0007ff, 0x10000706, 0x0,
3877 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3878 {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0,
3879 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3880 {VCMPGTSDCC, 0xfc0007ff, 0x100007c7, 0x0,
3881 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3882 {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0,
3883 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3884 {VCMPGTSHCC, 0xfc0007ff, 0x10000746, 0x0,
3885 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3886 {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0,
3887 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3888 {VCMPGTSWCC, 0xfc0007ff, 0x10000786, 0x0,
3889 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3890 {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0,
3891 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3892 {VCMPGTUBCC, 0xfc0007ff, 0x10000606, 0x0,
3893 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3894 {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0,
3895 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3896 {VCMPGTUDCC, 0xfc0007ff, 0x100006c7, 0x0,
3897 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3898 {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0,
3899 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3900 {VCMPGTUHCC, 0xfc0007ff, 0x10000646, 0x0,
3901 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3902 {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0,
3903 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3904 {VCMPGTUWCC, 0xfc0007ff, 0x10000686, 0x0,
3905 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3906 {VAND, 0xfc0007ff, 0x10000404, 0x0,
3907 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3908 {VANDC, 0xfc0007ff, 0x10000444, 0x0,
3909 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3910 {VEQV, 0xfc0007ff, 0x10000684, 0x0,
3911 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3912 {VNAND, 0xfc0007ff, 0x10000584, 0x0,
3913 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3914 {VORC, 0xfc0007ff, 0x10000544, 0x0,
3915 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3916 {VNOR, 0xfc0007ff, 0x10000504, 0x0,
3917 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3918 {VOR, 0xfc0007ff, 0x10000484, 0x0,
3919 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3920 {VXOR, 0xfc0007ff, 0x100004c4, 0x0,
3921 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3922 {VRLB, 0xfc0007ff, 0x10000004, 0x0,
3923 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3924 {VRLH, 0xfc0007ff, 0x10000044, 0x0,
3925 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3926 {VRLW, 0xfc0007ff, 0x10000084, 0x0,
3927 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3928 {VRLD, 0xfc0007ff, 0x100000c4, 0x0,
3929 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3930 {VSLB, 0xfc0007ff, 0x10000104, 0x0,
3931 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3932 {VSLH, 0xfc0007ff, 0x10000144, 0x0,
3933 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3934 {VSLW, 0xfc0007ff, 0x10000184, 0x0,
3935 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3936 {VSLD, 0xfc0007ff, 0x100005c4, 0x0,
3937 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3938 {VSRB, 0xfc0007ff, 0x10000204, 0x0,
3939 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3940 {VSRH, 0xfc0007ff, 0x10000244, 0x0,
3941 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3942 {VSRW, 0xfc0007ff, 0x10000284, 0x0,
3943 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3944 {VSRD, 0xfc0007ff, 0x100006c4, 0x0,
3945 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3946 {VSRAB, 0xfc0007ff, 0x10000304, 0x0,
3947 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3948 {VSRAH, 0xfc0007ff, 0x10000344, 0x0,
3949 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3950 {VSRAW, 0xfc0007ff, 0x10000384, 0x0,
3951 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3952 {VSRAD, 0xfc0007ff, 0x100003c4, 0x0,
3953 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3954 {VADDFP, 0xfc0007ff, 0x1000000a, 0x0,
3955 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3956 {VSUBFP, 0xfc0007ff, 0x1000004a, 0x0,
3957 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3958 {VMADDFP, 0xfc00003f, 0x1000002e, 0x0,
3959 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
3960 {VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0,
3961 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}},
3962 {VMAXFP, 0xfc0007ff, 0x1000040a, 0x0,
3963 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3964 {VMINFP, 0xfc0007ff, 0x1000044a, 0x0,
3965 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3966 {VCTSXS, 0xfc0007ff, 0x100003ca, 0x0,
3967 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
3968 {VCTUXS, 0xfc0007ff, 0x1000038a, 0x0,
3969 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
3970 {VCFSX, 0xfc0007ff, 0x1000034a, 0x0,
3971 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
3972 {VCFUX, 0xfc0007ff, 0x1000030a, 0x0,
3973 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}},
3974 {VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000,
3975 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3976 {VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000,
3977 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3978 {VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000,
3979 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3980 {VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000,
3981 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
3982 {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0,
3983 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3984 {VCMPBFPCC, 0xfc0007ff, 0x100007c6, 0x0,
3985 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3986 {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0,
3987 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3988 {VCMPEQFPCC, 0xfc0007ff, 0x100004c6, 0x0,
3989 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3990 {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0,
3991 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3992 {VCMPGEFPCC, 0xfc0007ff, 0x100005c6, 0x0,
3993 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3994 {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0,
3995 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3996 {VCMPGTFPCC, 0xfc0007ff, 0x100006c6, 0x0,
3997 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
3998 {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000,
3999 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4000 {VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000,
4001 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4002 {VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000,
4003 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4004 {VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000,
4005 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4006 {VCIPHER, 0xfc0007ff, 0x10000508, 0x0,
4007 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4008 {VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0,
4009 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4010 {VNCIPHER, 0xfc0007ff, 0x10000548, 0x0,
4011 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4012 {VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0,
4013 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4014 {VSBOX, 0xfc0007ff, 0x100005c8, 0xf800,
4015 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}},
4016 {VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0,
4017 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
4018 {VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0,
4019 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}},
4020 {VPMSUMB, 0xfc0007ff, 0x10000408, 0x0,
4021 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4022 {VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0,
4023 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4024 {VPMSUMH, 0xfc0007ff, 0x10000448, 0x0,
4025 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4026 {VPMSUMW, 0xfc0007ff, 0x10000488, 0x0,
4027 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4028 {VPERMXOR, 0xfc00003f, 0x1000002d, 0x0,
4029 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}},
4030 {VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000,
4031 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4032 {VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000,
4033 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4034 {VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000,
4035 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4036 {VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000,
4037 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4038 {VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000,
4039 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4040 {VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000,
4041 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4042 {VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000,
4043 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4044 {VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000,
4045 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4046 {VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000,
4047 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}},
4048 {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0,
4049 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}},
4050 {BCDADDCC, 0xfc0005ff, 0x10000401, 0x0,
4051 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
4052 {BCDSUBCC, 0xfc0005ff, 0x10000441, 0x0,
4053 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}},
4054 {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000,
4055 [5]*argField{ap_VecReg_16_20}},
4056 {MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800,
4057 [5]*argField{ap_VecReg_6_10}},
4058 {DADD, 0xfc0007ff, 0xec000004, 0x0,
4059 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4060 {DADDCC, 0xfc0007ff, 0xec000005, 0x0,
4061 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4062 {DSUB, 0xfc0007ff, 0xec000404, 0x0,
4063 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4064 {DSUBCC, 0xfc0007ff, 0xec000405, 0x0,
4065 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4066 {DMUL, 0xfc0007ff, 0xec000044, 0x0,
4067 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4068 {DMULCC, 0xfc0007ff, 0xec000045, 0x0,
4069 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4070 {DDIV, 0xfc0007ff, 0xec000444, 0x0,
4071 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4072 {DDIVCC, 0xfc0007ff, 0xec000445, 0x0,
4073 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4074 {DCMPU, 0xfc0007fe, 0xec000504, 0x600001,
4075 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
4076 {DCMPO, 0xfc0007fe, 0xec000104, 0x600001,
4077 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
4078 {DTSTDC, 0xfc0003fe, 0xec000184, 0x600001,
4079 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4080 {DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001,
4081 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4082 {DTSTEX, 0xfc0007fe, 0xec000144, 0x600001,
4083 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
4084 {DTSTSF, 0xfc0007fe, 0xec000544, 0x600001,
4085 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}},
4086 {DQUAI, 0xfc0001ff, 0xec000086, 0x0,
4087 [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4088 {DQUAICC, 0xfc0001ff, 0xec000087, 0x0,
4089 [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4090 {DQUA, 0xfc0001ff, 0xec000006, 0x0,
4091 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4092 {DQUACC, 0xfc0001ff, 0xec000007, 0x0,
4093 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4094 {DRRND, 0xfc0001ff, 0xec000046, 0x0,
4095 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4096 {DRRNDCC, 0xfc0001ff, 0xec000047, 0x0,
4097 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4098 {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000,
4099 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4100 {DRINTXCC, 0xfc0001ff, 0xec0000c7, 0x1e0000,
4101 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4102 {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000,
4103 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4104 {DRINTNCC, 0xfc0001ff, 0xec0001c7, 0x1e0000,
4105 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}},
4106 {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000,
4107 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4108 {DCTDPCC, 0xfc0007ff, 0xec000205, 0x1f0000,
4109 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4110 {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000,
4111 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4112 {DCTQPQCC, 0xfc0007ff, 0xfc000205, 0x1f0000,
4113 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4114 {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000,
4115 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4116 {DRSPCC, 0xfc0007ff, 0xec000605, 0x1f0000,
4117 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4118 {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000,
4119 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4120 {DRDPQCC, 0xfc0007ff, 0xfc000605, 0x1f0000,
4121 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4122 {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000,
4123 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4124 {DCFFIXCC, 0xfc0007ff, 0xec000645, 0x1f0000,
4125 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4126 {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000,
4127 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4128 {DCFFIXQCC, 0xfc0007ff, 0xfc000645, 0x1f0000,
4129 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4130 {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000,
4131 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4132 {DCTFIXCC, 0xfc0007ff, 0xec000245, 0x1f0000,
4133 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4134 {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000,
4135 [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
4136 {DDEDPDCC, 0xfc0007ff, 0xec000285, 0x70000,
4137 [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}},
4138 {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000,
4139 [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
4140 {DENBCDCC, 0xfc0007ff, 0xec000685, 0xf0000,
4141 [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}},
4142 {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000,
4143 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4144 {DXEXCC, 0xfc0007ff, 0xec0002c5, 0x1f0000,
4145 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}},
4146 {DIEX, 0xfc0007ff, 0xec0006c4, 0x0,
4147 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4148 {DIEXCC, 0xfc0007ff, 0xec0006c5, 0x0,
4149 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}},
4150 {DSCLI, 0xfc0003ff, 0xec000084, 0x0,
4151 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4152 {DSCLICC, 0xfc0003ff, 0xec000085, 0x0,
4153 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4154 {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0,
4155 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4156 {DSCRICC, 0xfc0003ff, 0xec0000c5, 0x0,
4157 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}},
4158 {LXSDX, 0xfc0007fe, 0x7c000498, 0x0,
4159 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4160 {LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0,
4161 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4162 {LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0,
4163 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4164 {LXSSPX, 0xfc0007fe, 0x7c000418, 0x0,
4165 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4166 {LXVD2X, 0xfc0007fe, 0x7c000698, 0x0,
4167 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4168 {LXVDSX, 0xfc0007fe, 0x7c000298, 0x0,
4169 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4170 {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0,
4171 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4172 {STXSDX, 0xfc0007fe, 0x7c000598, 0x0,
4173 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4174 {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0,
4175 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4176 {STXSSPX, 0xfc0007fe, 0x7c000518, 0x0,
4177 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4178 {STXVD2X, 0xfc0007fe, 0x7c000798, 0x0,
4179 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4180 {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0,
4181 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4182 {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000,
4183 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4184 {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0,
4185 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4186 {XSADDSP, 0xfc0007f8, 0xf0000000, 0x0,
4187 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4188 {XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001,
4189 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4190 {XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001,
4191 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4192 {XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0,
4193 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4194 {XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000,
4195 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4196 {XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000,
4197 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4198 {XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000,
4199 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4200 {XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000,
4201 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4202 {XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000,
4203 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4204 {XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000,
4205 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4206 {XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000,
4207 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4208 {XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000,
4209 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4210 {XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000,
4211 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4212 {XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000,
4213 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4214 {XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000,
4215 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4216 {XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000,
4217 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4218 {XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0,
4219 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4220 {XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0,
4221 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4222 {XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0,
4223 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4224 {XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0,
4225 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4226 {XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0,
4227 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4228 {XSMINDP, 0xfc0007f8, 0xf0000540, 0x0,
4229 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4230 {XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0,
4231 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4232 {XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0,
4233 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4234 {XSMULDP, 0xfc0007f8, 0xf0000180, 0x0,
4235 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4236 {XSMULSP, 0xfc0007f8, 0xf0000080, 0x0,
4237 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4238 {XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000,
4239 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4240 {XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000,
4241 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4242 {XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0,
4243 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4244 {XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0,
4245 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4246 {XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0,
4247 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4248 {XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0,
4249 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4250 {XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000,
4251 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4252 {XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000,
4253 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4254 {XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000,
4255 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4256 {XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000,
4257 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4258 {XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000,
4259 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4260 {XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000,
4261 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4262 {XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000,
4263 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4264 {XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000,
4265 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4266 {XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000,
4267 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4268 {XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000,
4269 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4270 {XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000,
4271 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4272 {XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000,
4273 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4274 {XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0,
4275 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4276 {XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0,
4277 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4278 {XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001,
4279 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4280 {XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001,
4281 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
4282 {XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000,
4283 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4284 {XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000,
4285 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4286 {XVADDDP, 0xfc0007f8, 0xf0000300, 0x0,
4287 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4288 {XVADDSP, 0xfc0007f8, 0xf0000200, 0x0,
4289 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4290 {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0,
4291 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4292 {XVCMPEQDPCC, 0xfc0007f8, 0xf0000718, 0x0,
4293 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4294 {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0,
4295 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4296 {XVCMPEQSPCC, 0xfc0007f8, 0xf0000618, 0x0,
4297 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4298 {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0,
4299 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4300 {XVCMPGEDPCC, 0xfc0007f8, 0xf0000798, 0x0,
4301 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4302 {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0,
4303 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4304 {XVCMPGESPCC, 0xfc0007f8, 0xf0000698, 0x0,
4305 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4306 {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0,
4307 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4308 {XVCMPGTDPCC, 0xfc0007f8, 0xf0000758, 0x0,
4309 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4310 {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0,
4311 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4312 {XVCMPGTSPCC, 0xfc0007f8, 0xf0000658, 0x0,
4313 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4314 {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0,
4315 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4316 {XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0,
4317 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4318 {XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000,
4319 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4320 {XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000,
4321 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4322 {XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000,
4323 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4324 {XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000,
4325 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4326 {XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000,
4327 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4328 {XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000,
4329 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4330 {XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000,
4331 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4332 {XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000,
4333 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4334 {XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000,
4335 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4336 {XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000,
4337 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4338 {XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000,
4339 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4340 {XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000,
4341 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4342 {XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000,
4343 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4344 {XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000,
4345 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4346 {XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000,
4347 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4348 {XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000,
4349 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4350 {XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000,
4351 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4352 {XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000,
4353 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4354 {XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0,
4355 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4356 {XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0,
4357 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4358 {XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0,
4359 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4360 {XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0,
4361 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4362 {XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0,
4363 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4364 {XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0,
4365 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4366 {XVMINDP, 0xfc0007f8, 0xf0000740, 0x0,
4367 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4368 {XVMINSP, 0xfc0007f8, 0xf0000640, 0x0,
4369 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4370 {XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0,
4371 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4372 {XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0,
4373 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4374 {XVMULDP, 0xfc0007f8, 0xf0000380, 0x0,
4375 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4376 {XVMULSP, 0xfc0007f8, 0xf0000280, 0x0,
4377 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4378 {XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000,
4379 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4380 {XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000,
4381 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4382 {XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000,
4383 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4384 {XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000,
4385 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4386 {XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0,
4387 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4388 {XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0,
4389 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4390 {XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0,
4391 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4392 {XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0,
4393 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4394 {XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000,
4395 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4396 {XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000,
4397 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4398 {XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000,
4399 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4400 {XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000,
4401 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4402 {XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000,
4403 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4404 {XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000,
4405 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4406 {XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000,
4407 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4408 {XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000,
4409 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4410 {XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000,
4411 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4412 {XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000,
4413 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4414 {XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000,
4415 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4416 {XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000,
4417 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4418 {XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000,
4419 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4420 {XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000,
4421 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4422 {XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000,
4423 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4424 {XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000,
4425 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}},
4426 {XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0,
4427 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4428 {XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0,
4429 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4430 {XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001,
4431 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4432 {XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001,
4433 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4434 {XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001,
4435 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
4436 {XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001,
4437 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}},
4438 {XXLAND, 0xfc0007f8, 0xf0000410, 0x0,
4439 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4440 {XXLANDC, 0xfc0007f8, 0xf0000450, 0x0,
4441 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4442 {XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0,
4443 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4444 {XXLNAND, 0xfc0007f8, 0xf0000590, 0x0,
4445 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4446 {XXLORC, 0xfc0007f8, 0xf0000550, 0x0,
4447 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4448 {XXLNOR, 0xfc0007f8, 0xf0000510, 0x0,
4449 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4450 {XXLOR, 0xfc0007f8, 0xf0000490, 0x0,
4451 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4452 {XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0,
4453 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4454 {XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0,
4455 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4456 {XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0,
4457 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}},
4458 {XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0,
4459 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
4460 {XXSEL, 0xfc000030, 0xf0000030, 0x0,
4461 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}},
4462 {XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0,
4463 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}},
4464 {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000,
4465 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}},
4466 {BRINC, 0xfc0007ff, 0x1000020f, 0x0,
4467 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4468 {EVABS, 0xfc0007ff, 0x10000208, 0xf800,
4469 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4470 {EVADDIW, 0xfc0007ff, 0x10000202, 0x0,
4471 [5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}},
4472 {EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800,
4473 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4474 {EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800,
4475 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4476 {EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800,
4477 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4478 {EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800,
4479 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4480 {EVADDW, 0xfc0007ff, 0x10000200, 0x0,
4481 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4482 {EVAND, 0xfc0007ff, 0x10000211, 0x0,
4483 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4484 {EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000,
4485 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4486 {EVANDC, 0xfc0007ff, 0x10000212, 0x0,
4487 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4488 {EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000,
4489 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4490 {EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000,
4491 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4492 {EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000,
4493 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4494 {EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000,
4495 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4496 {EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800,
4497 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4498 {EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800,
4499 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4500 {EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0,
4501 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4502 {EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0,
4503 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4504 {EVEQV, 0xfc0007ff, 0x10000219, 0x0,
4505 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4506 {EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800,
4507 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4508 {EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800,
4509 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4510 {EVLDD, 0xfc0007ff, 0x10000301, 0x0,
4511 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4512 {EVLDH, 0xfc0007ff, 0x10000305, 0x0,
4513 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4514 {EVLDDX, 0xfc0007ff, 0x10000300, 0x0,
4515 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4516 {EVLDHX, 0xfc0007ff, 0x10000304, 0x0,
4517 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4518 {EVLDW, 0xfc0007ff, 0x10000303, 0x0,
4519 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4520 {EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0,
4521 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4522 {EVLDWX, 0xfc0007ff, 0x10000302, 0x0,
4523 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4524 {EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0,
4525 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4526 {EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0,
4527 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4528 {EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0,
4529 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4530 {EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0,
4531 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4532 {EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0,
4533 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4534 {EVLWHE, 0xfc0007ff, 0x10000311, 0x0,
4535 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4536 {EVLWHOS, 0xfc0007ff, 0x10000317, 0x0,
4537 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4538 {EVLWHEX, 0xfc0007ff, 0x10000310, 0x0,
4539 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4540 {EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0,
4541 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4542 {EVLWHOU, 0xfc0007ff, 0x10000315, 0x0,
4543 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4544 {EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0,
4545 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4546 {EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0,
4547 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4548 {EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0,
4549 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4550 {EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0,
4551 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4552 {EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0,
4553 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4554 {EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0,
4555 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4556 {EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0,
4557 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4558 {EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0,
4559 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4560 {EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0,
4561 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4562 {EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0,
4563 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4564 {EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0,
4565 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4566 {EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0,
4567 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4568 {EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0,
4569 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4570 {EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0,
4571 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4572 {EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0,
4573 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4574 {EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0,
4575 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4576 {EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0,
4577 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4578 {EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0,
4579 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4580 {EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0,
4581 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4582 {EVMHESMI, 0xfc0007ff, 0x10000409, 0x0,
4583 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4584 {EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0,
4585 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4586 {EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0,
4587 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4588 {EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0,
4589 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4590 {EVMHESSF, 0xfc0007ff, 0x10000403, 0x0,
4591 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4592 {EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0,
4593 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4594 {EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0,
4595 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4596 {EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0,
4597 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4598 {EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0,
4599 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4600 {EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0,
4601 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4602 {EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0,
4603 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4604 {EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0,
4605 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4606 {EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0,
4607 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4608 {EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0,
4609 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4610 {EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0,
4611 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4612 {EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0,
4613 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4614 {EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0,
4615 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4616 {EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0,
4617 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4618 {EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0,
4619 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4620 {EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0,
4621 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4622 {EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0,
4623 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4624 {EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0,
4625 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4626 {EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0,
4627 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4628 {EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0,
4629 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4630 {EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0,
4631 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4632 {EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0,
4633 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4634 {EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0,
4635 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4636 {EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0,
4637 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4638 {EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0,
4639 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4640 {EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0,
4641 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4642 {EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0,
4643 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4644 {EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0,
4645 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4646 {EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0,
4647 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4648 {EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0,
4649 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4650 {EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0,
4651 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4652 {EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0,
4653 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4654 {EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0,
4655 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4656 {EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0,
4657 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4658 {EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0,
4659 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4660 {EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0,
4661 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4662 {EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0,
4663 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4664 {EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0,
4665 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4666 {EVMRA, 0xfc0007ff, 0x100004c4, 0xf800,
4667 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4668 {EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0,
4669 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4670 {EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0,
4671 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4672 {EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0,
4673 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4674 {EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0,
4675 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4676 {EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0,
4677 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4678 {EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0,
4679 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4680 {EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0,
4681 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4682 {EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0,
4683 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4684 {EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0,
4685 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4686 {EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0,
4687 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4688 {EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0,
4689 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4690 {EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0,
4691 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4692 {EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0,
4693 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4694 {EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0,
4695 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4696 {EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0,
4697 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4698 {EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0,
4699 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4700 {EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0,
4701 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4702 {EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0,
4703 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4704 {EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0,
4705 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4706 {EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0,
4707 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4708 {EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0,
4709 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4710 {EVMWSMI, 0xfc0007ff, 0x10000459, 0x0,
4711 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4712 {EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0,
4713 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4714 {EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0,
4715 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4716 {EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0,
4717 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4718 {EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0,
4719 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4720 {EVMWSSF, 0xfc0007ff, 0x10000453, 0x0,
4721 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4722 {EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0,
4723 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4724 {EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0,
4725 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4726 {EVMWUMI, 0xfc0007ff, 0x10000458, 0x0,
4727 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4728 {EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0,
4729 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4730 {EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0,
4731 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4732 {EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0,
4733 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4734 {EVNAND, 0xfc0007ff, 0x1000021e, 0x0,
4735 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4736 {EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0,
4737 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4738 {EVNEG, 0xfc0007ff, 0x10000209, 0xf800,
4739 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4740 {EVNOR, 0xfc0007ff, 0x10000218, 0x0,
4741 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4742 {EVORC, 0xfc0007ff, 0x1000021b, 0x0,
4743 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4744 {EVOR, 0xfc0007ff, 0x10000217, 0x0,
4745 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4746 {EVRLW, 0xfc0007ff, 0x10000228, 0x0,
4747 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4748 {EVRLWI, 0xfc0007ff, 0x1000022a, 0x0,
4749 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
4750 {EVSEL, 0xfc0007f8, 0x10000278, 0x0,
4751 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}},
4752 {EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800,
4753 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4754 {EVSLW, 0xfc0007ff, 0x10000224, 0x0,
4755 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4756 {EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800,
4757 [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
4758 {EVSRWIS, 0xfc0007ff, 0x10000223, 0x0,
4759 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
4760 {EVSLWI, 0xfc0007ff, 0x10000226, 0x0,
4761 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
4762 {EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800,
4763 [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}},
4764 {EVSRWIU, 0xfc0007ff, 0x10000222, 0x0,
4765 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}},
4766 {EVSRWS, 0xfc0007ff, 0x10000221, 0x0,
4767 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4768 {EVSTDD, 0xfc0007ff, 0x10000321, 0x0,
4769 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4770 {EVSRWU, 0xfc0007ff, 0x10000220, 0x0,
4771 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4772 {EVSTDDX, 0xfc0007ff, 0x10000320, 0x0,
4773 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4774 {EVSTDH, 0xfc0007ff, 0x10000325, 0x0,
4775 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4776 {EVSTDW, 0xfc0007ff, 0x10000323, 0x0,
4777 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4778 {EVSTDHX, 0xfc0007ff, 0x10000324, 0x0,
4779 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4780 {EVSTDWX, 0xfc0007ff, 0x10000322, 0x0,
4781 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4782 {EVSTWHE, 0xfc0007ff, 0x10000331, 0x0,
4783 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4784 {EVSTWHO, 0xfc0007ff, 0x10000335, 0x0,
4785 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4786 {EVSTWWE, 0xfc0007ff, 0x10000339, 0x0,
4787 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4788 {EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0,
4789 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4790 {EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0,
4791 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4792 {EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0,
4793 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4794 {EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0,
4795 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}},
4796 {EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800,
4797 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4798 {EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0,
4799 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4800 {EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800,
4801 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4802 {EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800,
4803 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4804 {EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800,
4805 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4806 {EVSUBFW, 0xfc0007ff, 0x10000204, 0x0,
4807 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4808 {EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0,
4809 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}},
4810 {EVXOR, 0xfc0007ff, 0x10000216, 0x0,
4811 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4812 {EVFSABS, 0xfc0007ff, 0x10000284, 0xf800,
4813 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4814 {EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800,
4815 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4816 {EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800,
4817 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4818 {EVFSADD, 0xfc0007ff, 0x10000280, 0x0,
4819 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4820 {EVFSMUL, 0xfc0007ff, 0x10000288, 0x0,
4821 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4822 {EVFSSUB, 0xfc0007ff, 0x10000281, 0x0,
4823 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4824 {EVFSDIV, 0xfc0007ff, 0x10000289, 0x0,
4825 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4826 {EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000,
4827 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4828 {EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000,
4829 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4830 {EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000,
4831 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4832 {EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000,
4833 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4834 {EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000,
4835 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4836 {EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000,
4837 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4838 {EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000,
4839 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4840 {EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000,
4841 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4842 {EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000,
4843 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4844 {EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000,
4845 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4846 {EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000,
4847 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4848 {EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000,
4849 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4850 {EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000,
4851 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4852 {EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000,
4853 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4854 {EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000,
4855 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4856 {EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000,
4857 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4858 {EFSABS, 0xfc0007ff, 0x100002c4, 0xf800,
4859 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4860 {EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800,
4861 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4862 {EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800,
4863 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4864 {EFSADD, 0xfc0007ff, 0x100002c0, 0x0,
4865 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4866 {EFSMUL, 0xfc0007ff, 0x100002c8, 0x0,
4867 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4868 {EFSSUB, 0xfc0007ff, 0x100002c1, 0x0,
4869 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4870 {EFSDIV, 0xfc0007ff, 0x100002c9, 0x0,
4871 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4872 {EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000,
4873 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4874 {EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000,
4875 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4876 {EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000,
4877 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4878 {EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000,
4879 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4880 {EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000,
4881 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4882 {EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000,
4883 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4884 {EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000,
4885 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4886 {EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000,
4887 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4888 {EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000,
4889 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4890 {EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000,
4891 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4892 {EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000,
4893 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4894 {EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000,
4895 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4896 {EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000,
4897 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4898 {EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000,
4899 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4900 {EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000,
4901 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4902 {EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000,
4903 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4904 {EFDABS, 0xfc0007ff, 0x100002e4, 0xf800,
4905 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4906 {EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800,
4907 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4908 {EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800,
4909 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
4910 {EFDADD, 0xfc0007ff, 0x100002e0, 0x0,
4911 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4912 {EFDMUL, 0xfc0007ff, 0x100002e8, 0x0,
4913 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4914 {EFDSUB, 0xfc0007ff, 0x100002e1, 0x0,
4915 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4916 {EFDDIV, 0xfc0007ff, 0x100002e9, 0x0,
4917 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4918 {EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000,
4919 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4920 {EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000,
4921 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4922 {EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000,
4923 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4924 {EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000,
4925 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4926 {EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000,
4927 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4928 {EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000,
4929 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4930 {EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000,
4931 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
4932 {EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000,
4933 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4934 {EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000,
4935 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4936 {EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000,
4937 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4938 {EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000,
4939 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4940 {EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000,
4941 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4942 {EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000,
4943 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4944 {EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000,
4945 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4946 {EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000,
4947 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4948 {EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000,
4949 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4950 {EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000,
4951 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4952 {EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000,
4953 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4954 {EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000,
4955 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4956 {EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000,
4957 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4958 {EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000,
4959 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4960 {EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000,
4961 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
4962 {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0,
4963 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
4964 {DLMZBCC, 0xfc0007ff, 0x7c00009d, 0x0,
4965 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
4966 {MACCHW, 0xfc0007ff, 0x10000158, 0x0,
4967 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4968 {MACCHWCC, 0xfc0007ff, 0x10000159, 0x0,
4969 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4970 {MACCHWO, 0xfc0007ff, 0x10000558, 0x0,
4971 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4972 {MACCHWOCC, 0xfc0007ff, 0x10000559, 0x0,
4973 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4974 {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0,
4975 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4976 {MACCHWSCC, 0xfc0007ff, 0x100001d9, 0x0,
4977 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4978 {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0,
4979 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4980 {MACCHWSOCC, 0xfc0007ff, 0x100005d9, 0x0,
4981 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4982 {MACCHWU, 0xfc0007ff, 0x10000118, 0x0,
4983 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4984 {MACCHWUCC, 0xfc0007ff, 0x10000119, 0x0,
4985 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4986 {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0,
4987 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4988 {MACCHWUOCC, 0xfc0007ff, 0x10000519, 0x0,
4989 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4990 {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0,
4991 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4992 {MACCHWSUCC, 0xfc0007ff, 0x10000199, 0x0,
4993 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4994 {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0,
4995 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4996 {MACCHWSUOCC, 0xfc0007ff, 0x10000599, 0x0,
4997 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
4998 {MACHHW, 0xfc0007ff, 0x10000058, 0x0,
4999 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5000 {MACHHWCC, 0xfc0007ff, 0x10000059, 0x0,
5001 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5002 {MACHHWO, 0xfc0007ff, 0x10000458, 0x0,
5003 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5004 {MACHHWOCC, 0xfc0007ff, 0x10000459, 0x0,
5005 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5006 {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0,
5007 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5008 {MACHHWSCC, 0xfc0007ff, 0x100000d9, 0x0,
5009 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5010 {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0,
5011 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5012 {MACHHWSOCC, 0xfc0007ff, 0x100004d9, 0x0,
5013 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5014 {MACHHWU, 0xfc0007ff, 0x10000018, 0x0,
5015 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5016 {MACHHWUCC, 0xfc0007ff, 0x10000019, 0x0,
5017 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5018 {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0,
5019 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5020 {MACHHWUOCC, 0xfc0007ff, 0x10000419, 0x0,
5021 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5022 {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0,
5023 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5024 {MACHHWSUCC, 0xfc0007ff, 0x10000099, 0x0,
5025 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5026 {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0,
5027 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5028 {MACHHWSUOCC, 0xfc0007ff, 0x10000499, 0x0,
5029 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5030 {MACLHW, 0xfc0007ff, 0x10000358, 0x0,
5031 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5032 {MACLHWCC, 0xfc0007ff, 0x10000359, 0x0,
5033 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5034 {MACLHWO, 0xfc0007ff, 0x10000758, 0x0,
5035 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5036 {MACLHWOCC, 0xfc0007ff, 0x10000759, 0x0,
5037 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5038 {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0,
5039 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5040 {MACLHWSCC, 0xfc0007ff, 0x100003d9, 0x0,
5041 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5042 {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0,
5043 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5044 {MACLHWSOCC, 0xfc0007ff, 0x100007d9, 0x0,
5045 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5046 {MACLHWU, 0xfc0007ff, 0x10000318, 0x0,
5047 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5048 {MACLHWUCC, 0xfc0007ff, 0x10000319, 0x0,
5049 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5050 {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0,
5051 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5052 {MACLHWUOCC, 0xfc0007ff, 0x10000719, 0x0,
5053 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5054 {MULCHW, 0xfc0007ff, 0x10000150, 0x0,
5055 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5056 {MULCHWCC, 0xfc0007ff, 0x10000151, 0x0,
5057 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5058 {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0,
5059 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5060 {MACLHWSUCC, 0xfc0007ff, 0x10000399, 0x0,
5061 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5062 {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0,
5063 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5064 {MACLHWSUOCC, 0xfc0007ff, 0x10000799, 0x0,
5065 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5066 {MULCHWU, 0xfc0007ff, 0x10000110, 0x0,
5067 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5068 {MULCHWUCC, 0xfc0007ff, 0x10000111, 0x0,
5069 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5070 {MULHHW, 0xfc0007ff, 0x10000050, 0x0,
5071 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5072 {MULHHWCC, 0xfc0007ff, 0x10000051, 0x0,
5073 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5074 {MULLHW, 0xfc0007ff, 0x10000350, 0x0,
5075 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5076 {MULLHWCC, 0xfc0007ff, 0x10000351, 0x0,
5077 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5078 {MULHHWU, 0xfc0007ff, 0x10000010, 0x0,
5079 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5080 {MULHHWUCC, 0xfc0007ff, 0x10000011, 0x0,
5081 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5082 {MULLHWU, 0xfc0007ff, 0x10000310, 0x0,
5083 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5084 {MULLHWUCC, 0xfc0007ff, 0x10000311, 0x0,
5085 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5086 {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0,
5087 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5088 {NMACCHWCC, 0xfc0007ff, 0x1000015d, 0x0,
5089 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5090 {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0,
5091 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5092 {NMACCHWOCC, 0xfc0007ff, 0x1000055d, 0x0,
5093 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5094 {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0,
5095 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5096 {NMACCHWSCC, 0xfc0007ff, 0x100001dd, 0x0,
5097 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5098 {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0,
5099 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5100 {NMACCHWSOCC, 0xfc0007ff, 0x100005dd, 0x0,
5101 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5102 {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0,
5103 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5104 {NMACHHWCC, 0xfc0007ff, 0x1000005d, 0x0,
5105 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5106 {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0,
5107 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5108 {NMACHHWOCC, 0xfc0007ff, 0x1000045d, 0x0,
5109 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5110 {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0,
5111 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5112 {NMACHHWSCC, 0xfc0007ff, 0x100000dd, 0x0,
5113 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5114 {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0,
5115 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5116 {NMACHHWSOCC, 0xfc0007ff, 0x100004dd, 0x0,
5117 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5118 {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0,
5119 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5120 {NMACLHWCC, 0xfc0007ff, 0x1000035d, 0x0,
5121 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5122 {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0,
5123 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5124 {NMACLHWOCC, 0xfc0007ff, 0x1000075d, 0x0,
5125 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5126 {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0,
5127 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5128 {NMACLHWSCC, 0xfc0007ff, 0x100003dd, 0x0,
5129 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5130 {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0,
5131 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5132 {NMACLHWSOCC, 0xfc0007ff, 0x100007dd, 0x0,
5133 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5134 {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001,
5135 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5136 {ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001,
5137 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5138 {DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001,
5139 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5140 {DCBT, 0xfc0007fe, 0x7c00022c, 0x1,
5141 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
5142 {DCBT, 0xfc0007fe, 0x7c00022c, 0x1,
5143 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5144 {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1,
5145 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}},
5146 {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1,
5147 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5148 {DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001,
5149 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5150 {DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001,
5151 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5152 {DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001,
5153 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
5154 {ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801,
5155 [5]*argField{}},
5156 {LBARX, 0xfc0007ff, 0x7c000068, 0x0,
5157 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5158 {LBARX, 0xfc0007fe, 0x7c000068, 0x0,
5159 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
5160 {LHARX, 0xfc0007ff, 0x7c0000e8, 0x0,
5161 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5162 {LHARX, 0xfc0007fe, 0x7c0000e8, 0x0,
5163 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
5164 {LWARX, 0xfc0007ff, 0x7c000028, 0x0,
5165 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5166 {LWARX, 0xfc0007ff, 0x7c000028, 0x0,
5167 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5168 {LWARX, 0xfc0007fe, 0x7c000028, 0x0,
5169 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
5170 {STBCXCC, 0xfc0007ff, 0x7c00056d, 0x0,
5171 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5172 {STHCXCC, 0xfc0007ff, 0x7c0005ad, 0x0,
5173 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5174 {STWCXCC, 0xfc0007ff, 0x7c00012d, 0x0,
5175 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5176 {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0,
5177 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5178 {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0,
5179 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
5180 {STDCXCC, 0xfc0007ff, 0x7c0001ad, 0x0,
5181 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5182 {LQARX, 0xfc0007ff, 0x7c000228, 0x0,
5183 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5184 {LQARX, 0xfc0007fe, 0x7c000228, 0x0,
5185 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}},
5186 {STQCXCC, 0xfc0007ff, 0x7c00016d, 0x0,
5187 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5188 {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801,
5189 [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}},
5190 {EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801,
5191 [5]*argField{}},
5192 {MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801,
5193 [5]*argField{ap_ImmUnsigned_6_10}},
5194 {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801,
5195 [5]*argField{ap_ImmUnsigned_9_10}},
5196 {TBEGINCC, 0xfc0007ff, 0x7c00051d, 0x1dff800,
5197 [5]*argField{ap_ImmUnsigned_10_10}},
5198 {TENDCC, 0xfc0007ff, 0x7c00055d, 0x1fff800,
5199 [5]*argField{ap_ImmUnsigned_6_6}},
5200 {TABORTCC, 0xfc0007ff, 0x7c00071d, 0x3e0f800,
5201 [5]*argField{ap_Reg_11_15}},
5202 {TABORTWCCC, 0xfc0007ff, 0x7c00061d, 0x0,
5203 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5204 {TABORTWCICC, 0xfc0007ff, 0x7c00069d, 0x0,
5205 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
5206 {TABORTDCCC, 0xfc0007ff, 0x7c00065d, 0x0,
5207 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5208 {TABORTDCICC, 0xfc0007ff, 0x7c0006dd, 0x0,
5209 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}},
5210 {TSRCC, 0xfc0007ff, 0x7c0005dd, 0x3dff800,
5211 [5]*argField{ap_ImmUnsigned_10_10}},
5212 {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801,
5213 [5]*argField{ap_CondRegField_6_8}},
5214 {MFTB, 0xfc0007fe, 0x7c0002e6, 0x1,
5215 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
5216 {RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001,
5217 [5]*argField{ap_ImmUnsigned_20_20}},
5218 {LBDX, 0xfc0007fe, 0x7c000406, 0x1,
5219 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5220 {LHDX, 0xfc0007fe, 0x7c000446, 0x1,
5221 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5222 {LWDX, 0xfc0007fe, 0x7c000486, 0x1,
5223 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5224 {LDDX, 0xfc0007fe, 0x7c0004c6, 0x1,
5225 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5226 {LFDDX, 0xfc0007fe, 0x7c000646, 0x1,
5227 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5228 {STBDX, 0xfc0007fe, 0x7c000506, 0x1,
5229 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5230 {STHDX, 0xfc0007fe, 0x7c000546, 0x1,
5231 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5232 {STWDX, 0xfc0007fe, 0x7c000586, 0x1,
5233 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5234 {STDDX, 0xfc0007fe, 0x7c0005c6, 0x1,
5235 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5236 {STFDDX, 0xfc0007fe, 0x7c000746, 0x1,
5237 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5238 {DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001,
5239 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5240 {ECIWX, 0xfc0007fe, 0x7c00026c, 0x1,
5241 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5242 {ECOWX, 0xfc0007fe, 0x7c00036c, 0x1,
5243 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5244 {SC, 0xfc000002, 0x44000002, 0x3fff01d,
5245 [5]*argField{ap_ImmUnsigned_20_26}},
5246 {RFID, 0xfc0007fe, 0x4c000024, 0x3fff801,
5247 [5]*argField{}},
5248 {HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801,
5249 [5]*argField{}},
5250 {DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801,
5251 [5]*argField{}},
5252 {NAP, 0xfc0007fe, 0x4c000364, 0x3fff801,
5253 [5]*argField{}},
5254 {SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801,
5255 [5]*argField{}},
5256 {RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801,
5257 [5]*argField{}},
5258 {LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1,
5259 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5260 {LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1,
5261 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5262 {LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1,
5263 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5264 {LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1,
5265 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5266 {STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1,
5267 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5268 {STWCIX, 0xfc0007fe, 0x7c00072a, 0x1,
5269 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5270 {STHCIX, 0xfc0007fe, 0x7c00076a, 0x1,
5271 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5272 {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1,
5273 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5274 {TRECLAIMCC, 0xfc0007ff, 0x7c00075d, 0x3e0f800,
5275 [5]*argField{ap_Reg_11_15}},
5276 {TRECHKPTCC, 0xfc0007ff, 0x7c0007dd, 0x3fff800,
5277 [5]*argField{}},
5278 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1,
5279 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
5280 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1,
5281 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
5282 {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801,
5283 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
5284 {MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801,
5285 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}},
5286 {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801,
5287 [5]*argField{ap_Reg_6_10}},
5288 {SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001,
5289 [5]*argField{ap_Reg_16_20}},
5290 {SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801,
5291 [5]*argField{ap_ImmUnsigned_8_10}},
5292 {SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001,
5293 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5294 {SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001,
5295 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5296 {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001,
5297 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5298 {SLBFEECC, 0xfc0007ff, 0x7c0007a7, 0x1f0000,
5299 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5300 {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801,
5301 [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}},
5302 {MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001,
5303 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5304 {MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801,
5305 [5]*argField{ap_Reg_6_10, ap_SpReg_12_15}},
5306 {MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001,
5307 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}},
5308 {TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001,
5309 [5]*argField{ap_Reg_16_20, ap_Reg_6_10}},
5310 {TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001,
5311 [5]*argField{ap_Reg_16_20}},
5312 {TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801,
5313 [5]*argField{}},
5314 {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801,
5315 [5]*argField{}},
5316 {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001,
5317 [5]*argField{ap_Reg_16_20}},
5318 {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001,
5319 [5]*argField{ap_Reg_16_20}},
5320 {MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001,
5321 [5]*argField{ap_Reg_16_20}},
5322 {MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001,
5323 [5]*argField{ap_Reg_16_20}},
5324 {MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1,
5325 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
5326 {SC, 0xfc000002, 0x44000002, 0x3fffffd,
5327 [5]*argField{}},
5328 {RFI, 0xfc0007fe, 0x4c000064, 0x3fff801,
5329 [5]*argField{}},
5330 {RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801,
5331 [5]*argField{}},
5332 {RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801,
5333 [5]*argField{}},
5334 {RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801,
5335 [5]*argField{}},
5336 {RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801,
5337 [5]*argField{}},
5338 {EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1,
5339 [5]*argField{ap_ImmUnsigned_6_20}},
5340 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1,
5341 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
5342 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1,
5343 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
5344 {MTDCR, 0xfc0007fe, 0x7c000386, 0x1,
5345 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}},
5346 {MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801,
5347 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}},
5348 {MFDCR, 0xfc0007fe, 0x7c000286, 0x1,
5349 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}},
5350 {MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801,
5351 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}},
5352 {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801,
5353 [5]*argField{ap_Reg_6_10}},
5354 {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801,
5355 [5]*argField{ap_Reg_6_10}},
5356 {WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801,
5357 [5]*argField{ap_Reg_6_10}},
5358 {WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801,
5359 [5]*argField{ap_ImmUnsigned_16_16}},
5360 {LBEPX, 0xfc0007fe, 0x7c0000be, 0x1,
5361 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5362 {LHEPX, 0xfc0007fe, 0x7c00023e, 0x1,
5363 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5364 {LWEPX, 0xfc0007fe, 0x7c00003e, 0x1,
5365 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5366 {LDEPX, 0xfc0007fe, 0x7c00003a, 0x1,
5367 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5368 {STBEPX, 0xfc0007fe, 0x7c0001be, 0x1,
5369 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5370 {STHEPX, 0xfc0007fe, 0x7c00033e, 0x1,
5371 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5372 {STWEPX, 0xfc0007fe, 0x7c00013e, 0x1,
5373 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5374 {STDEPX, 0xfc0007fe, 0x7c00013a, 0x1,
5375 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5376 {DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001,
5377 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5378 {DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1,
5379 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5380 {DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001,
5381 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}},
5382 {DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1,
5383 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5384 {ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001,
5385 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5386 {DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001,
5387 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5388 {LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1,
5389 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5390 {STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1,
5391 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5392 {EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1,
5393 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5394 {EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1,
5395 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5396 {LVEPX, 0xfc0007fe, 0x7c00024e, 0x1,
5397 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5398 {LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1,
5399 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5400 {STVEPX, 0xfc0007fe, 0x7c00064e, 0x1,
5401 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5402 {STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1,
5403 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5404 {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001,
5405 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5406 {DCBLQCC, 0xfc0007ff, 0x7c00034d, 0x2000000,
5407 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5408 {ICBLQCC, 0xfc0007ff, 0x7c00018d, 0x2000000,
5409 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5410 {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001,
5411 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5412 {DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001,
5413 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5414 {ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001,
5415 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5416 {ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001,
5417 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5418 {DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001,
5419 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}},
5420 {TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001,
5421 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5422 {TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001,
5423 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5424 {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001,
5425 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5426 {TLBSRXCC, 0xfc0007ff, 0x7c0006a5, 0x3e00000,
5427 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5428 {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801,
5429 [5]*argField{}},
5430 {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801,
5431 [5]*argField{}},
5432 {TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801,
5433 [5]*argField{}},
5434 {DNH, 0xfc0007fe, 0x4c00018c, 0x1,
5435 [5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}},
5436 {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001,
5437 [5]*argField{ap_Reg_16_20}},
5438 {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001,
5439 [5]*argField{ap_Reg_16_20}},
5440 {DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801,
5441 [5]*argField{ap_ImmUnsigned_7_10}},
5442 {ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801,
5443 [5]*argField{ap_ImmUnsigned_7_10}},
5444 {DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1,
5445 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5446 {ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001,
5447 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5448 {MFPMR, 0xfc0007fe, 0x7c00029c, 0x1,
5449 [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}},
5450 {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1,
5451 [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}},
5452 {ADDEX, 0xfc0001fe, 0x7c000154, 0x1,
5453 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_21_22}},
5454 {DARN, 0xfc0007fe, 0x7c0005e6, 0x1cf801,
5455 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_14_15}},
5456 {MADDHD, 0xfc00003f, 0x10000030, 0x0,
5457 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
5458 {MADDHDU, 0xfc00003f, 0x10000031, 0x0,
5459 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
5460 {MADDLD, 0xfc00003f, 0x10000033, 0x0,
5461 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_Reg_21_25}},
5462 {CMPRB, 0xfc0007fe, 0x7c000180, 0x400001,
5463 [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_10_10, ap_Reg_11_15, ap_Reg_16_20}},
5464 {CMPEQB, 0xfc0007fe, 0x7c0001c0, 0x600001,
5465 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}},
5466 {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1,
5467 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}},
5468 {EXTSWSLI, 0xfc0007fd, 0x7c0006f4, 0x0,
5469 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
5470 {EXTSWSLICC, 0xfc0007fd, 0x7c0006f5, 0x0,
5471 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}},
5472 {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800,
5473 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
5474 {MFVSRLD, 0xfc0007fe, 0x7c000266, 0xf800,
5475 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
5476 {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800,
5477 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}},
5478 {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800,
5479 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
5480 {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800,
5481 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
5482 {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800,
5483 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
5484 {MTVSRDD, 0xfc0007fe, 0x7c000366, 0x0,
5485 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}},
5486 {MTVSRWS, 0xfc0007fe, 0x7c000326, 0xf800,
5487 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}},
5488 {MCRXRX, 0xfc0007fe, 0x7c000480, 0x7ff801,
5489 [5]*argField{ap_CondRegField_6_8}},
5490 {COPY, 0xfc2007fe, 0x7c20060c, 0x3c00001,
5491 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5492 {PASTECC, 0xfc2007ff, 0x7c20070d, 0x3c00000,
5493 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}},
5494 }
5495
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