Source file src/pkg/cmd/internal/obj/s390x/asmz.go
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 package s390x
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "fmt"
36 "log"
37 "math"
38 "sort"
39 )
40
41
42
43
44 type ctxtz struct {
45 ctxt *obj.Link
46 newprog obj.ProgAlloc
47 cursym *obj.LSym
48 autosize int32
49 instoffset int64
50 pc int64
51 }
52
53
54 const (
55 funcAlign = 16
56 )
57
58 type Optab struct {
59 as obj.As
60 i uint8
61 a1 uint8
62 a2 uint8
63 a3 uint8
64 a4 uint8
65 a5 uint8
66 a6 uint8
67 }
68
69 var optab = []Optab{
70
71 {i: 0, as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE},
72 {i: 0, as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE},
73 {i: 0, as: obj.APCDATA, a1: C_LCON, a6: C_LCON},
74 {i: 0, as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR},
75 {i: 0, as: obj.ANOP},
76 {i: 0, as: obj.ANOP, a1: C_SAUTO},
77
78
79 {i: 1, as: AMOVD, a1: C_REG, a6: C_REG},
80 {i: 1, as: AMOVB, a1: C_REG, a6: C_REG},
81 {i: 1, as: AMOVBZ, a1: C_REG, a6: C_REG},
82 {i: 1, as: AMOVW, a1: C_REG, a6: C_REG},
83 {i: 1, as: AMOVWZ, a1: C_REG, a6: C_REG},
84 {i: 1, as: AFMOVD, a1: C_FREG, a6: C_FREG},
85 {i: 1, as: AMOVDBR, a1: C_REG, a6: C_REG},
86
87
88 {i: 26, as: AMOVD, a1: C_LACON, a6: C_REG},
89 {i: 26, as: AMOVW, a1: C_LACON, a6: C_REG},
90 {i: 26, as: AMOVWZ, a1: C_LACON, a6: C_REG},
91 {i: 3, as: AMOVD, a1: C_DCON, a6: C_REG},
92 {i: 3, as: AMOVW, a1: C_DCON, a6: C_REG},
93 {i: 3, as: AMOVWZ, a1: C_DCON, a6: C_REG},
94 {i: 3, as: AMOVB, a1: C_DCON, a6: C_REG},
95 {i: 3, as: AMOVBZ, a1: C_DCON, a6: C_REG},
96
97
98 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LAUTO},
99 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LAUTO},
100 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LAUTO},
101 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LAUTO},
102 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LAUTO},
103 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LAUTO},
104 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LAUTO},
105 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LAUTO},
106 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LAUTO},
107 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LAUTO},
108 {i: 72, as: AMOVD, a1: C_SCON, a6: C_LOREG},
109 {i: 72, as: AMOVD, a1: C_ADDCON, a6: C_LOREG},
110 {i: 72, as: AMOVW, a1: C_SCON, a6: C_LOREG},
111 {i: 72, as: AMOVW, a1: C_ADDCON, a6: C_LOREG},
112 {i: 72, as: AMOVWZ, a1: C_SCON, a6: C_LOREG},
113 {i: 72, as: AMOVWZ, a1: C_ADDCON, a6: C_LOREG},
114 {i: 72, as: AMOVB, a1: C_SCON, a6: C_LOREG},
115 {i: 72, as: AMOVB, a1: C_ADDCON, a6: C_LOREG},
116 {i: 72, as: AMOVBZ, a1: C_SCON, a6: C_LOREG},
117 {i: 72, as: AMOVBZ, a1: C_ADDCON, a6: C_LOREG},
118
119
120 {i: 35, as: AMOVD, a1: C_REG, a6: C_LAUTO},
121 {i: 35, as: AMOVW, a1: C_REG, a6: C_LAUTO},
122 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LAUTO},
123 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LAUTO},
124 {i: 35, as: AMOVB, a1: C_REG, a6: C_LAUTO},
125 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LAUTO},
126 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LAUTO},
127 {i: 35, as: AMOVD, a1: C_REG, a6: C_LOREG},
128 {i: 35, as: AMOVW, a1: C_REG, a6: C_LOREG},
129 {i: 35, as: AMOVWZ, a1: C_REG, a6: C_LOREG},
130 {i: 35, as: AMOVBZ, a1: C_REG, a6: C_LOREG},
131 {i: 35, as: AMOVB, a1: C_REG, a6: C_LOREG},
132 {i: 35, as: AMOVDBR, a1: C_REG, a6: C_LOREG},
133 {i: 35, as: AMOVHBR, a1: C_REG, a6: C_LOREG},
134 {i: 74, as: AMOVD, a1: C_REG, a6: C_ADDR},
135 {i: 74, as: AMOVW, a1: C_REG, a6: C_ADDR},
136 {i: 74, as: AMOVWZ, a1: C_REG, a6: C_ADDR},
137 {i: 74, as: AMOVBZ, a1: C_REG, a6: C_ADDR},
138 {i: 74, as: AMOVB, a1: C_REG, a6: C_ADDR},
139
140
141 {i: 36, as: AMOVD, a1: C_LAUTO, a6: C_REG},
142 {i: 36, as: AMOVW, a1: C_LAUTO, a6: C_REG},
143 {i: 36, as: AMOVWZ, a1: C_LAUTO, a6: C_REG},
144 {i: 36, as: AMOVBZ, a1: C_LAUTO, a6: C_REG},
145 {i: 36, as: AMOVB, a1: C_LAUTO, a6: C_REG},
146 {i: 36, as: AMOVDBR, a1: C_LAUTO, a6: C_REG},
147 {i: 36, as: AMOVHBR, a1: C_LAUTO, a6: C_REG},
148 {i: 36, as: AMOVD, a1: C_LOREG, a6: C_REG},
149 {i: 36, as: AMOVW, a1: C_LOREG, a6: C_REG},
150 {i: 36, as: AMOVWZ, a1: C_LOREG, a6: C_REG},
151 {i: 36, as: AMOVBZ, a1: C_LOREG, a6: C_REG},
152 {i: 36, as: AMOVB, a1: C_LOREG, a6: C_REG},
153 {i: 36, as: AMOVDBR, a1: C_LOREG, a6: C_REG},
154 {i: 36, as: AMOVHBR, a1: C_LOREG, a6: C_REG},
155 {i: 75, as: AMOVD, a1: C_ADDR, a6: C_REG},
156 {i: 75, as: AMOVW, a1: C_ADDR, a6: C_REG},
157 {i: 75, as: AMOVWZ, a1: C_ADDR, a6: C_REG},
158 {i: 75, as: AMOVBZ, a1: C_ADDR, a6: C_REG},
159 {i: 75, as: AMOVB, a1: C_ADDR, a6: C_REG},
160
161
162 {i: 99, as: ALAAG, a1: C_REG, a2: C_REG, a6: C_LOREG},
163
164
165 {i: 2, as: AADD, a1: C_REG, a2: C_REG, a6: C_REG},
166 {i: 2, as: AADD, a1: C_REG, a6: C_REG},
167 {i: 22, as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG},
168 {i: 22, as: AADD, a1: C_LCON, a6: C_REG},
169 {i: 12, as: AADD, a1: C_LOREG, a6: C_REG},
170 {i: 12, as: AADD, a1: C_LAUTO, a6: C_REG},
171 {i: 21, as: ASUB, a1: C_LCON, a2: C_REG, a6: C_REG},
172 {i: 21, as: ASUB, a1: C_LCON, a6: C_REG},
173 {i: 12, as: ASUB, a1: C_LOREG, a6: C_REG},
174 {i: 12, as: ASUB, a1: C_LAUTO, a6: C_REG},
175 {i: 4, as: AMULHD, a1: C_REG, a6: C_REG},
176 {i: 4, as: AMULHD, a1: C_REG, a2: C_REG, a6: C_REG},
177 {i: 2, as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG},
178 {i: 2, as: ADIVW, a1: C_REG, a6: C_REG},
179 {i: 10, as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG},
180 {i: 10, as: ASUB, a1: C_REG, a6: C_REG},
181 {i: 47, as: ANEG, a1: C_REG, a6: C_REG},
182 {i: 47, as: ANEG, a6: C_REG},
183
184
185 {i: 6, as: AAND, a1: C_REG, a2: C_REG, a6: C_REG},
186 {i: 6, as: AAND, a1: C_REG, a6: C_REG},
187 {i: 23, as: AAND, a1: C_LCON, a6: C_REG},
188 {i: 12, as: AAND, a1: C_LOREG, a6: C_REG},
189 {i: 12, as: AAND, a1: C_LAUTO, a6: C_REG},
190 {i: 6, as: AANDW, a1: C_REG, a2: C_REG, a6: C_REG},
191 {i: 6, as: AANDW, a1: C_REG, a6: C_REG},
192 {i: 24, as: AANDW, a1: C_LCON, a6: C_REG},
193 {i: 12, as: AANDW, a1: C_LOREG, a6: C_REG},
194 {i: 12, as: AANDW, a1: C_LAUTO, a6: C_REG},
195 {i: 7, as: ASLD, a1: C_REG, a6: C_REG},
196 {i: 7, as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG},
197 {i: 7, as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG},
198 {i: 7, as: ASLD, a1: C_SCON, a6: C_REG},
199 {i: 13, as: ARNSBG, a1: C_SCON, a3: C_SCON, a4: C_SCON, a5: C_REG, a6: C_REG},
200
201
202 {i: 79, as: ACSG, a1: C_REG, a2: C_REG, a6: C_SOREG},
203
204
205 {i: 32, as: AFADD, a1: C_FREG, a6: C_FREG},
206 {i: 33, as: AFABS, a1: C_FREG, a6: C_FREG},
207 {i: 33, as: AFABS, a6: C_FREG},
208 {i: 34, as: AFMADD, a1: C_FREG, a2: C_FREG, a6: C_FREG},
209 {i: 32, as: AFMUL, a1: C_FREG, a6: C_FREG},
210 {i: 36, as: AFMOVD, a1: C_LAUTO, a6: C_FREG},
211 {i: 36, as: AFMOVD, a1: C_LOREG, a6: C_FREG},
212 {i: 75, as: AFMOVD, a1: C_ADDR, a6: C_FREG},
213 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LAUTO},
214 {i: 35, as: AFMOVD, a1: C_FREG, a6: C_LOREG},
215 {i: 74, as: AFMOVD, a1: C_FREG, a6: C_ADDR},
216 {i: 67, as: AFMOVD, a1: C_ZCON, a6: C_FREG},
217 {i: 81, as: ALDGR, a1: C_REG, a6: C_FREG},
218 {i: 81, as: ALGDR, a1: C_FREG, a6: C_REG},
219 {i: 82, as: ACEFBRA, a1: C_REG, a6: C_FREG},
220 {i: 83, as: ACFEBRA, a1: C_FREG, a6: C_REG},
221 {i: 48, as: AFIEBR, a1: C_SCON, a2: C_FREG, a6: C_FREG},
222 {i: 49, as: ACPSDR, a1: C_FREG, a2: C_FREG, a6: C_FREG},
223 {i: 50, as: ALTDBR, a1: C_FREG, a6: C_FREG},
224 {i: 51, as: ATCDB, a1: C_FREG, a6: C_SCON},
225
226
227 {i: 19, as: AMOVD, a1: C_SYMADDR, a6: C_REG},
228 {i: 93, as: AMOVD, a1: C_GOTADDR, a6: C_REG},
229 {i: 94, as: AMOVD, a1: C_TLS_LE, a6: C_REG},
230 {i: 95, as: AMOVD, a1: C_TLS_IE, a6: C_REG},
231
232
233 {i: 5, as: ASYSCALL},
234 {i: 77, as: ASYSCALL, a1: C_SCON},
235
236
237 {i: 16, as: ABEQ, a6: C_SBRA},
238 {i: 11, as: ABR, a6: C_LBRA},
239 {i: 16, as: ABC, a1: C_SCON, a2: C_REG, a6: C_LBRA},
240 {i: 18, as: ABR, a6: C_REG},
241 {i: 18, as: ABR, a1: C_REG, a6: C_REG},
242 {i: 15, as: ABR, a6: C_ZOREG},
243 {i: 15, as: ABC, a6: C_ZOREG},
244 {i: 89, as: ACMPBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
245 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_ADDCON, a6: C_SBRA},
246 {i: 90, as: ACMPBEQ, a1: C_REG, a3: C_SCON, a6: C_SBRA},
247 {i: 89, as: ACMPUBEQ, a1: C_REG, a2: C_REG, a6: C_SBRA},
248 {i: 90, as: ACMPUBEQ, a1: C_REG, a3: C_ANDCON, a6: C_SBRA},
249
250
251 {i: 17, as: AMOVDEQ, a1: C_REG, a6: C_REG},
252
253
254 {i: 8, as: AFLOGR, a1: C_REG, a6: C_REG},
255
256
257 {i: 9, as: APOPCNT, a1: C_REG, a6: C_REG},
258
259
260 {i: 70, as: ACMP, a1: C_REG, a6: C_REG},
261 {i: 71, as: ACMP, a1: C_REG, a6: C_LCON},
262 {i: 70, as: ACMPU, a1: C_REG, a6: C_REG},
263 {i: 71, as: ACMPU, a1: C_REG, a6: C_LCON},
264 {i: 70, as: AFCMPO, a1: C_FREG, a6: C_FREG},
265 {i: 70, as: AFCMPO, a1: C_FREG, a2: C_REG, a6: C_FREG},
266
267
268 {i: 91, as: ATMHH, a1: C_REG, a6: C_ANDCON},
269
270
271 {i: 92, as: AIPM, a1: C_REG},
272
273
274 {i: 68, as: AMOVW, a1: C_AREG, a6: C_REG},
275 {i: 68, as: AMOVWZ, a1: C_AREG, a6: C_REG},
276 {i: 69, as: AMOVW, a1: C_REG, a6: C_AREG},
277 {i: 69, as: AMOVWZ, a1: C_REG, a6: C_AREG},
278
279
280 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LOREG},
281 {i: 96, as: ACLEAR, a1: C_LCON, a6: C_LAUTO},
282
283
284 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LOREG},
285 {i: 97, as: ASTMG, a1: C_REG, a2: C_REG, a6: C_LAUTO},
286 {i: 98, as: ALMG, a1: C_LOREG, a2: C_REG, a6: C_REG},
287 {i: 98, as: ALMG, a1: C_LAUTO, a2: C_REG, a6: C_REG},
288
289
290 {i: 40, as: ABYTE, a1: C_SCON},
291 {i: 40, as: AWORD, a1: C_LCON},
292 {i: 31, as: ADWORD, a1: C_LCON},
293 {i: 31, as: ADWORD, a1: C_DCON},
294
295
296 {i: 80, as: ASYNC},
297
298
299 {i: 88, as: ASTCK, a6: C_SAUTO},
300 {i: 88, as: ASTCK, a6: C_SOREG},
301
302
303 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LOREG},
304 {i: 84, as: AMVC, a1: C_SCON, a3: C_LOREG, a6: C_LAUTO},
305 {i: 84, as: AMVC, a1: C_SCON, a3: C_LAUTO, a6: C_LAUTO},
306
307
308 {i: 85, as: ALARL, a1: C_LCON, a6: C_REG},
309 {i: 85, as: ALARL, a1: C_SYMADDR, a6: C_REG},
310 {i: 86, as: ALA, a1: C_SOREG, a6: C_REG},
311 {i: 86, as: ALA, a1: C_SAUTO, a6: C_REG},
312 {i: 87, as: AEXRL, a1: C_SYMADDR, a6: C_REG},
313
314
315 {i: 78, as: obj.AUNDEF},
316
317
318
319
320 {i: 100, as: AVST, a1: C_VREG, a6: C_SOREG},
321 {i: 100, as: AVST, a1: C_VREG, a6: C_SAUTO},
322 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
323 {i: 100, as: AVSTEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
324
325
326 {i: 101, as: AVL, a1: C_SOREG, a6: C_VREG},
327 {i: 101, as: AVL, a1: C_SAUTO, a6: C_VREG},
328 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
329 {i: 101, as: AVLEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
330
331
332 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SOREG},
333 {i: 102, as: AVSCEG, a1: C_SCON, a2: C_VREG, a6: C_SAUTO},
334
335
336 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SOREG, a6: C_VREG},
337 {i: 103, as: AVGEG, a1: C_SCON, a3: C_SAUTO, a6: C_VREG},
338
339
340 {i: 104, as: AVESLG, a1: C_SCON, a2: C_VREG, a6: C_VREG},
341 {i: 104, as: AVESLG, a1: C_REG, a2: C_VREG, a6: C_VREG},
342 {i: 104, as: AVESLG, a1: C_SCON, a6: C_VREG},
343 {i: 104, as: AVESLG, a1: C_REG, a6: C_VREG},
344 {i: 104, as: AVLGVG, a1: C_SCON, a2: C_VREG, a6: C_REG},
345 {i: 104, as: AVLGVG, a1: C_REG, a2: C_VREG, a6: C_REG},
346 {i: 104, as: AVLVGG, a1: C_SCON, a2: C_REG, a6: C_VREG},
347 {i: 104, as: AVLVGG, a1: C_REG, a2: C_REG, a6: C_VREG},
348
349
350 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SOREG},
351 {i: 105, as: AVSTM, a1: C_VREG, a2: C_VREG, a6: C_SAUTO},
352
353
354 {i: 106, as: AVLM, a1: C_SOREG, a2: C_VREG, a6: C_VREG},
355 {i: 106, as: AVLM, a1: C_SAUTO, a2: C_VREG, a6: C_VREG},
356
357
358 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SOREG},
359 {i: 107, as: AVSTL, a1: C_REG, a2: C_VREG, a6: C_SAUTO},
360
361
362 {i: 108, as: AVLL, a1: C_REG, a3: C_SOREG, a6: C_VREG},
363 {i: 108, as: AVLL, a1: C_REG, a3: C_SAUTO, a6: C_VREG},
364
365
366 {i: 109, as: AVGBM, a1: C_ANDCON, a6: C_VREG},
367 {i: 109, as: AVZERO, a6: C_VREG},
368 {i: 109, as: AVREPIG, a1: C_ADDCON, a6: C_VREG},
369 {i: 109, as: AVREPIG, a1: C_SCON, a6: C_VREG},
370 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_ADDCON, a6: C_VREG},
371 {i: 109, as: AVLEIG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
372
373
374 {i: 110, as: AVGMG, a1: C_SCON, a3: C_SCON, a6: C_VREG},
375
376
377 {i: 111, as: AVREPG, a1: C_UCON, a2: C_VREG, a6: C_VREG},
378
379
380
381 {i: 112, as: AVERIMG, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
382 {i: 112, as: AVSLDB, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
383
384
385 {i: 113, as: AVFTCIDB, a1: C_SCON, a2: C_VREG, a6: C_VREG},
386
387
388 {i: 114, as: AVLR, a1: C_VREG, a6: C_VREG},
389
390
391 {i: 115, as: AVECG, a1: C_VREG, a6: C_VREG},
392
393
394 {i: 117, as: AVCEQG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
395 {i: 117, as: AVFAEF, a1: C_VREG, a2: C_VREG, a6: C_VREG},
396 {i: 117, as: AVPKSG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
397
398
399 {i: 118, as: AVAQ, a1: C_VREG, a2: C_VREG, a6: C_VREG},
400 {i: 118, as: AVAQ, a1: C_VREG, a6: C_VREG},
401 {i: 118, as: AVNOT, a1: C_VREG, a6: C_VREG},
402 {i: 123, as: AVPDI, a1: C_SCON, a2: C_VREG, a3: C_VREG, a6: C_VREG},
403
404
405 {i: 119, as: AVERLLVG, a1: C_VREG, a2: C_VREG, a6: C_VREG},
406 {i: 119, as: AVERLLVG, a1: C_VREG, a6: C_VREG},
407
408
409 {i: 120, as: AVACQ, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
410
411
412 {i: 121, as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG},
413
414
415 {i: 122, as: AVLVGP, a1: C_REG, a2: C_REG, a6: C_VREG},
416 }
417
418 var oprange [ALAST & obj.AMask][]Optab
419
420 var xcmp [C_NCLASS][C_NCLASS]bool
421
422 func spanz(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
423 p := cursym.Func.Text
424 if p == nil || p.Link == nil {
425 return
426 }
427
428 if oprange[AORW&obj.AMask] == nil {
429 ctxt.Diag("s390x ops not initialized, call s390x.buildop first")
430 }
431
432 c := ctxtz{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
433
434 buffer := make([]byte, 0)
435 changed := true
436 loop := 0
437 for changed {
438 if loop > 100 {
439 c.ctxt.Diag("stuck in spanz loop")
440 break
441 }
442 changed = false
443 buffer = buffer[:0]
444 c.cursym.R = make([]obj.Reloc, 0)
445 for p := c.cursym.Func.Text; p != nil; p = p.Link {
446 pc := int64(len(buffer))
447 if pc != p.Pc {
448 changed = true
449 }
450 p.Pc = pc
451 c.pc = p.Pc
452 c.asmout(p, &buffer)
453 if pc == int64(len(buffer)) {
454 switch p.As {
455 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA, obj.ATEXT:
456
457 default:
458 c.ctxt.Diag("zero-width instruction\n%v", p)
459 }
460 }
461 }
462 loop++
463 }
464
465 c.cursym.Size = int64(len(buffer))
466 if c.cursym.Size%funcAlign != 0 {
467 c.cursym.Size += funcAlign - (c.cursym.Size % funcAlign)
468 }
469 c.cursym.Grow(c.cursym.Size)
470 copy(c.cursym.P, buffer)
471 }
472
473 func isint32(v int64) bool {
474 return int64(int32(v)) == v
475 }
476
477 func isuint32(v uint64) bool {
478 return uint64(uint32(v)) == v
479 }
480
481 func (c *ctxtz) aclass(a *obj.Addr) int {
482 switch a.Type {
483 case obj.TYPE_NONE:
484 return C_NONE
485
486 case obj.TYPE_REG:
487 if REG_R0 <= a.Reg && a.Reg <= REG_R15 {
488 return C_REG
489 }
490 if REG_F0 <= a.Reg && a.Reg <= REG_F15 {
491 return C_FREG
492 }
493 if REG_AR0 <= a.Reg && a.Reg <= REG_AR15 {
494 return C_AREG
495 }
496 if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
497 return C_VREG
498 }
499 return C_GOK
500
501 case obj.TYPE_MEM:
502 switch a.Name {
503 case obj.NAME_EXTERN,
504 obj.NAME_STATIC:
505 if a.Sym == nil {
506
507 break
508 }
509 c.instoffset = a.Offset
510 if a.Sym.Type == objabi.STLSBSS {
511 if c.ctxt.Flag_shared {
512 return C_TLS_IE
513 }
514 return C_TLS_LE
515 }
516 return C_ADDR
517
518 case obj.NAME_GOTREF:
519 return C_GOTADDR
520
521 case obj.NAME_AUTO:
522 if a.Reg == REGSP {
523
524
525 a.Reg = obj.REG_NONE
526 }
527 c.instoffset = int64(c.autosize) + a.Offset
528 if c.instoffset >= -BIG && c.instoffset < BIG {
529 return C_SAUTO
530 }
531 return C_LAUTO
532
533 case obj.NAME_PARAM:
534 if a.Reg == REGSP {
535
536
537 a.Reg = obj.REG_NONE
538 }
539 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
540 if c.instoffset >= -BIG && c.instoffset < BIG {
541 return C_SAUTO
542 }
543 return C_LAUTO
544
545 case obj.NAME_NONE:
546 c.instoffset = a.Offset
547 if c.instoffset == 0 {
548 return C_ZOREG
549 }
550 if c.instoffset >= -BIG && c.instoffset < BIG {
551 return C_SOREG
552 }
553 return C_LOREG
554 }
555
556 return C_GOK
557
558 case obj.TYPE_TEXTSIZE:
559 return C_TEXTSIZE
560
561 case obj.TYPE_FCONST:
562 if f64, ok := a.Val.(float64); ok && math.Float64bits(f64) == 0 {
563 return C_ZCON
564 }
565 c.ctxt.Diag("cannot handle the floating point constant %v", a.Val)
566
567 case obj.TYPE_CONST,
568 obj.TYPE_ADDR:
569 switch a.Name {
570 case obj.NAME_NONE:
571 c.instoffset = a.Offset
572 if a.Reg != 0 {
573 if -BIG <= c.instoffset && c.instoffset <= BIG {
574 return C_SACON
575 }
576 if isint32(c.instoffset) {
577 return C_LACON
578 }
579 return C_DACON
580 }
581
582 case obj.NAME_EXTERN,
583 obj.NAME_STATIC:
584 s := a.Sym
585 if s == nil {
586 return C_GOK
587 }
588 c.instoffset = a.Offset
589
590 return C_SYMADDR
591
592 case obj.NAME_AUTO:
593 if a.Reg == REGSP {
594
595
596 a.Reg = obj.REG_NONE
597 }
598 c.instoffset = int64(c.autosize) + a.Offset
599 if c.instoffset >= -BIG && c.instoffset < BIG {
600 return C_SACON
601 }
602 return C_LACON
603
604 case obj.NAME_PARAM:
605 if a.Reg == REGSP {
606
607
608 a.Reg = obj.REG_NONE
609 }
610 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
611 if c.instoffset >= -BIG && c.instoffset < BIG {
612 return C_SACON
613 }
614 return C_LACON
615
616 default:
617 return C_GOK
618 }
619
620 if c.instoffset == 0 {
621 return C_ZCON
622 }
623 if c.instoffset >= 0 {
624 if c.instoffset <= 0x7fff {
625 return C_SCON
626 }
627 if c.instoffset <= 0xffff {
628 return C_ANDCON
629 }
630 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) {
631 return C_UCON
632 }
633 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
634 return C_LCON
635 }
636 return C_DCON
637 }
638
639 if c.instoffset >= -0x8000 {
640 return C_ADDCON
641 }
642 if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
643 return C_UCON
644 }
645 if isint32(c.instoffset) {
646 return C_LCON
647 }
648 return C_DCON
649
650 case obj.TYPE_BRANCH:
651 return C_SBRA
652 }
653
654 return C_GOK
655 }
656
657 func (c *ctxtz) oplook(p *obj.Prog) *Optab {
658
659 if p.Optab != 0 {
660 return &optab[p.Optab-1]
661 }
662 if len(p.RestArgs) > 3 {
663 c.ctxt.Diag("too many RestArgs: got %v, maximum is 3\n", len(p.RestArgs))
664 return nil
665 }
666
667
668 p.From.Class = int8(c.aclass(&p.From) + 1)
669 p.To.Class = int8(c.aclass(&p.To) + 1)
670 for i := range p.RestArgs {
671 p.RestArgs[i].Class = int8(c.aclass(&p.RestArgs[i]) + 1)
672 }
673
674
675 args := [...]int8{
676 p.From.Class - 1,
677 C_NONE,
678 C_NONE,
679 C_NONE,
680 C_NONE,
681 p.To.Class - 1,
682 }
683
684 switch {
685 case REG_R0 <= p.Reg && p.Reg <= REG_R15:
686 args[1] = C_REG
687 case REG_V0 <= p.Reg && p.Reg <= REG_V31:
688 args[1] = C_VREG
689 case REG_F0 <= p.Reg && p.Reg <= REG_F15:
690 args[1] = C_FREG
691 case REG_AR0 <= p.Reg && p.Reg <= REG_AR15:
692 args[1] = C_AREG
693 }
694
695 for i, a := range p.RestArgs {
696 args[2+i] = a.Class - 1
697 }
698
699
700 ops := oprange[p.As&obj.AMask]
701 cmp := [len(args)]*[C_NCLASS]bool{}
702 for i := range cmp {
703 cmp[i] = &xcmp[args[i]]
704 }
705 for i := range ops {
706 op := &ops[i]
707 if cmp[0][op.a1] && cmp[1][op.a2] &&
708 cmp[2][op.a3] && cmp[3][op.a4] &&
709 cmp[4][op.a5] && cmp[5][op.a6] {
710 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
711 return op
712 }
713 }
714
715
716 s := ""
717 for _, a := range args {
718 s += fmt.Sprintf(" %v", DRconv(int(a)))
719 }
720 c.ctxt.Diag("illegal combination %v%v\n", p.As, s)
721 c.ctxt.Diag("prog: %v\n", p)
722 return nil
723 }
724
725 func cmp(a int, b int) bool {
726 if a == b {
727 return true
728 }
729 switch a {
730 case C_DCON:
731 if b == C_LCON {
732 return true
733 }
734 fallthrough
735 case C_LCON:
736 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
737 return true
738 }
739
740 case C_ADDCON:
741 if b == C_ZCON || b == C_SCON {
742 return true
743 }
744
745 case C_ANDCON:
746 if b == C_ZCON || b == C_SCON {
747 return true
748 }
749
750 case C_UCON:
751 if b == C_ZCON || b == C_SCON {
752 return true
753 }
754
755 case C_SCON:
756 if b == C_ZCON {
757 return true
758 }
759
760 case C_LACON:
761 if b == C_SACON {
762 return true
763 }
764
765 case C_LBRA:
766 if b == C_SBRA {
767 return true
768 }
769
770 case C_LAUTO:
771 if b == C_SAUTO {
772 return true
773 }
774
775 case C_LOREG:
776 if b == C_ZOREG || b == C_SOREG {
777 return true
778 }
779
780 case C_SOREG:
781 if b == C_ZOREG {
782 return true
783 }
784
785 case C_ANY:
786 return true
787 }
788
789 return false
790 }
791
792 type ocmp []Optab
793
794 func (x ocmp) Len() int {
795 return len(x)
796 }
797
798 func (x ocmp) Swap(i, j int) {
799 x[i], x[j] = x[j], x[i]
800 }
801
802 func (x ocmp) Less(i, j int) bool {
803 p1 := &x[i]
804 p2 := &x[j]
805 n := int(p1.as) - int(p2.as)
806 if n != 0 {
807 return n < 0
808 }
809 n = int(p1.a1) - int(p2.a1)
810 if n != 0 {
811 return n < 0
812 }
813 n = int(p1.a2) - int(p2.a2)
814 if n != 0 {
815 return n < 0
816 }
817 n = int(p1.a3) - int(p2.a3)
818 if n != 0 {
819 return n < 0
820 }
821 n = int(p1.a4) - int(p2.a4)
822 if n != 0 {
823 return n < 0
824 }
825 return false
826 }
827 func opset(a, b obj.As) {
828 oprange[a&obj.AMask] = oprange[b&obj.AMask]
829 }
830
831 func buildop(ctxt *obj.Link) {
832 if oprange[AORW&obj.AMask] != nil {
833
834
835
836 return
837 }
838
839 for i := 0; i < C_NCLASS; i++ {
840 for n := 0; n < C_NCLASS; n++ {
841 if cmp(n, i) {
842 xcmp[i][n] = true
843 }
844 }
845 }
846 sort.Sort(ocmp(optab))
847 for i := 0; i < len(optab); i++ {
848 r := optab[i].as
849 start := i
850 for ; i+1 < len(optab); i++ {
851 if optab[i+1].as != r {
852 break
853 }
854 }
855 oprange[r&obj.AMask] = optab[start : i+1]
856
857
858
859 switch r {
860 case AADD:
861 opset(AADDC, r)
862 opset(AADDW, r)
863 opset(AMULLD, r)
864 opset(AMULLW, r)
865 case ADIVW:
866 opset(AADDE, r)
867 opset(ADIVD, r)
868 opset(ADIVDU, r)
869 opset(ADIVWU, r)
870 opset(AMODD, r)
871 opset(AMODDU, r)
872 opset(AMODW, r)
873 opset(AMODWU, r)
874 case AMULHD:
875 opset(AMULHDU, r)
876 case AMOVBZ:
877 opset(AMOVH, r)
878 opset(AMOVHZ, r)
879 case ALA:
880 opset(ALAY, r)
881 case AMVC:
882 opset(ACLC, r)
883 opset(AXC, r)
884 opset(AOC, r)
885 opset(ANC, r)
886 case ASTCK:
887 opset(ASTCKC, r)
888 opset(ASTCKE, r)
889 opset(ASTCKF, r)
890 case ALAAG:
891 opset(ALAA, r)
892 opset(ALAAL, r)
893 opset(ALAALG, r)
894 opset(ALAN, r)
895 opset(ALANG, r)
896 opset(ALAX, r)
897 opset(ALAXG, r)
898 opset(ALAO, r)
899 opset(ALAOG, r)
900 case ASTMG:
901 opset(ASTMY, r)
902 case ALMG:
903 opset(ALMY, r)
904 case ABEQ:
905 opset(ABGE, r)
906 opset(ABGT, r)
907 opset(ABLE, r)
908 opset(ABLT, r)
909 opset(ABNE, r)
910 opset(ABVC, r)
911 opset(ABVS, r)
912 opset(ABLEU, r)
913 opset(ABLTU, r)
914 case ABR:
915 opset(ABL, r)
916 case ABC:
917 opset(ABCL, r)
918 case AFABS:
919 opset(AFNABS, r)
920 opset(ALPDFR, r)
921 opset(ALNDFR, r)
922 opset(AFNEG, r)
923 opset(AFNEGS, r)
924 opset(ALEDBR, r)
925 opset(ALDEBR, r)
926 opset(AFSQRT, r)
927 opset(AFSQRTS, r)
928 case AFADD:
929 opset(AFADDS, r)
930 opset(AFDIV, r)
931 opset(AFDIVS, r)
932 opset(AFSUB, r)
933 opset(AFSUBS, r)
934 case AFMADD:
935 opset(AFMADDS, r)
936 opset(AFMSUB, r)
937 opset(AFMSUBS, r)
938 case AFMUL:
939 opset(AFMULS, r)
940 case AFCMPO:
941 opset(AFCMPU, r)
942 opset(ACEBR, r)
943 case AAND:
944 opset(AOR, r)
945 opset(AXOR, r)
946 case AANDW:
947 opset(AORW, r)
948 opset(AXORW, r)
949 case ASLD:
950 opset(ASRD, r)
951 opset(ASLW, r)
952 opset(ASRW, r)
953 opset(ASRAD, r)
954 opset(ASRAW, r)
955 opset(ARLL, r)
956 opset(ARLLG, r)
957 case ARNSBG:
958 opset(ARXSBG, r)
959 opset(AROSBG, r)
960 opset(ARNSBGT, r)
961 opset(ARXSBGT, r)
962 opset(AROSBGT, r)
963 opset(ARISBG, r)
964 opset(ARISBGN, r)
965 opset(ARISBGZ, r)
966 opset(ARISBGNZ, r)
967 opset(ARISBHG, r)
968 opset(ARISBLG, r)
969 opset(ARISBHGZ, r)
970 opset(ARISBLGZ, r)
971 case ACSG:
972 opset(ACS, r)
973 case ASUB:
974 opset(ASUBC, r)
975 opset(ASUBE, r)
976 opset(ASUBW, r)
977 case ANEG:
978 opset(ANEGW, r)
979 case AFMOVD:
980 opset(AFMOVS, r)
981 case AMOVDBR:
982 opset(AMOVWBR, r)
983 case ACMP:
984 opset(ACMPW, r)
985 case ACMPU:
986 opset(ACMPWU, r)
987 case ATMHH:
988 opset(ATMHL, r)
989 opset(ATMLH, r)
990 opset(ATMLL, r)
991 case ACEFBRA:
992 opset(ACDFBRA, r)
993 opset(ACEGBRA, r)
994 opset(ACDGBRA, r)
995 opset(ACELFBR, r)
996 opset(ACDLFBR, r)
997 opset(ACELGBR, r)
998 opset(ACDLGBR, r)
999 case ACFEBRA:
1000 opset(ACFDBRA, r)
1001 opset(ACGEBRA, r)
1002 opset(ACGDBRA, r)
1003 opset(ACLFEBR, r)
1004 opset(ACLFDBR, r)
1005 opset(ACLGEBR, r)
1006 opset(ACLGDBR, r)
1007 case AFIEBR:
1008 opset(AFIDBR, r)
1009 case ACMPBEQ:
1010 opset(ACMPBGE, r)
1011 opset(ACMPBGT, r)
1012 opset(ACMPBLE, r)
1013 opset(ACMPBLT, r)
1014 opset(ACMPBNE, r)
1015 case ACMPUBEQ:
1016 opset(ACMPUBGE, r)
1017 opset(ACMPUBGT, r)
1018 opset(ACMPUBLE, r)
1019 opset(ACMPUBLT, r)
1020 opset(ACMPUBNE, r)
1021 case AMOVDEQ:
1022 opset(AMOVDGE, r)
1023 opset(AMOVDGT, r)
1024 opset(AMOVDLE, r)
1025 opset(AMOVDLT, r)
1026 opset(AMOVDNE, r)
1027 case ALTDBR:
1028 opset(ALTEBR, r)
1029 case ATCDB:
1030 opset(ATCEB, r)
1031 case AVL:
1032 opset(AVLLEZB, r)
1033 opset(AVLLEZH, r)
1034 opset(AVLLEZF, r)
1035 opset(AVLLEZG, r)
1036 opset(AVLREPB, r)
1037 opset(AVLREPH, r)
1038 opset(AVLREPF, r)
1039 opset(AVLREPG, r)
1040 case AVLEG:
1041 opset(AVLBB, r)
1042 opset(AVLEB, r)
1043 opset(AVLEH, r)
1044 opset(AVLEF, r)
1045 opset(AVLEG, r)
1046 opset(AVLREP, r)
1047 case AVSTEG:
1048 opset(AVSTEB, r)
1049 opset(AVSTEH, r)
1050 opset(AVSTEF, r)
1051 case AVSCEG:
1052 opset(AVSCEF, r)
1053 case AVGEG:
1054 opset(AVGEF, r)
1055 case AVESLG:
1056 opset(AVESLB, r)
1057 opset(AVESLH, r)
1058 opset(AVESLF, r)
1059 opset(AVERLLB, r)
1060 opset(AVERLLH, r)
1061 opset(AVERLLF, r)
1062 opset(AVERLLG, r)
1063 opset(AVESRAB, r)
1064 opset(AVESRAH, r)
1065 opset(AVESRAF, r)
1066 opset(AVESRAG, r)
1067 opset(AVESRLB, r)
1068 opset(AVESRLH, r)
1069 opset(AVESRLF, r)
1070 opset(AVESRLG, r)
1071 case AVLGVG:
1072 opset(AVLGVB, r)
1073 opset(AVLGVH, r)
1074 opset(AVLGVF, r)
1075 case AVLVGG:
1076 opset(AVLVGB, r)
1077 opset(AVLVGH, r)
1078 opset(AVLVGF, r)
1079 case AVZERO:
1080 opset(AVONE, r)
1081 case AVREPIG:
1082 opset(AVREPIB, r)
1083 opset(AVREPIH, r)
1084 opset(AVREPIF, r)
1085 case AVLEIG:
1086 opset(AVLEIB, r)
1087 opset(AVLEIH, r)
1088 opset(AVLEIF, r)
1089 case AVGMG:
1090 opset(AVGMB, r)
1091 opset(AVGMH, r)
1092 opset(AVGMF, r)
1093 case AVREPG:
1094 opset(AVREPB, r)
1095 opset(AVREPH, r)
1096 opset(AVREPF, r)
1097 case AVERIMG:
1098 opset(AVERIMB, r)
1099 opset(AVERIMH, r)
1100 opset(AVERIMF, r)
1101 case AVFTCIDB:
1102 opset(AWFTCIDB, r)
1103 case AVLR:
1104 opset(AVUPHB, r)
1105 opset(AVUPHH, r)
1106 opset(AVUPHF, r)
1107 opset(AVUPLHB, r)
1108 opset(AVUPLHH, r)
1109 opset(AVUPLHF, r)
1110 opset(AVUPLB, r)
1111 opset(AVUPLHW, r)
1112 opset(AVUPLF, r)
1113 opset(AVUPLLB, r)
1114 opset(AVUPLLH, r)
1115 opset(AVUPLLF, r)
1116 opset(AVCLZB, r)
1117 opset(AVCLZH, r)
1118 opset(AVCLZF, r)
1119 opset(AVCLZG, r)
1120 opset(AVCTZB, r)
1121 opset(AVCTZH, r)
1122 opset(AVCTZF, r)
1123 opset(AVCTZG, r)
1124 opset(AVLDEB, r)
1125 opset(AWLDEB, r)
1126 opset(AVFLCDB, r)
1127 opset(AWFLCDB, r)
1128 opset(AVFLNDB, r)
1129 opset(AWFLNDB, r)
1130 opset(AVFLPDB, r)
1131 opset(AWFLPDB, r)
1132 opset(AVFSQDB, r)
1133 opset(AWFSQDB, r)
1134 opset(AVISTRB, r)
1135 opset(AVISTRH, r)
1136 opset(AVISTRF, r)
1137 opset(AVISTRBS, r)
1138 opset(AVISTRHS, r)
1139 opset(AVISTRFS, r)
1140 opset(AVLCB, r)
1141 opset(AVLCH, r)
1142 opset(AVLCF, r)
1143 opset(AVLCG, r)
1144 opset(AVLPB, r)
1145 opset(AVLPH, r)
1146 opset(AVLPF, r)
1147 opset(AVLPG, r)
1148 opset(AVPOPCT, r)
1149 opset(AVSEGB, r)
1150 opset(AVSEGH, r)
1151 opset(AVSEGF, r)
1152 case AVECG:
1153 opset(AVECB, r)
1154 opset(AVECH, r)
1155 opset(AVECF, r)
1156 opset(AVECLB, r)
1157 opset(AVECLH, r)
1158 opset(AVECLF, r)
1159 opset(AVECLG, r)
1160 opset(AWFCDB, r)
1161 opset(AWFKDB, r)
1162 case AVCEQG:
1163 opset(AVCEQB, r)
1164 opset(AVCEQH, r)
1165 opset(AVCEQF, r)
1166 opset(AVCEQBS, r)
1167 opset(AVCEQHS, r)
1168 opset(AVCEQFS, r)
1169 opset(AVCEQGS, r)
1170 opset(AVCHB, r)
1171 opset(AVCHH, r)
1172 opset(AVCHF, r)
1173 opset(AVCHG, r)
1174 opset(AVCHBS, r)
1175 opset(AVCHHS, r)
1176 opset(AVCHFS, r)
1177 opset(AVCHGS, r)
1178 opset(AVCHLB, r)
1179 opset(AVCHLH, r)
1180 opset(AVCHLF, r)
1181 opset(AVCHLG, r)
1182 opset(AVCHLBS, r)
1183 opset(AVCHLHS, r)
1184 opset(AVCHLFS, r)
1185 opset(AVCHLGS, r)
1186 case AVFAEF:
1187 opset(AVFAEB, r)
1188 opset(AVFAEH, r)
1189 opset(AVFAEBS, r)
1190 opset(AVFAEHS, r)
1191 opset(AVFAEFS, r)
1192 opset(AVFAEZB, r)
1193 opset(AVFAEZH, r)
1194 opset(AVFAEZF, r)
1195 opset(AVFAEZBS, r)
1196 opset(AVFAEZHS, r)
1197 opset(AVFAEZFS, r)
1198 opset(AVFEEB, r)
1199 opset(AVFEEH, r)
1200 opset(AVFEEF, r)
1201 opset(AVFEEBS, r)
1202 opset(AVFEEHS, r)
1203 opset(AVFEEFS, r)
1204 opset(AVFEEZB, r)
1205 opset(AVFEEZH, r)
1206 opset(AVFEEZF, r)
1207 opset(AVFEEZBS, r)
1208 opset(AVFEEZHS, r)
1209 opset(AVFEEZFS, r)
1210 opset(AVFENEB, r)
1211 opset(AVFENEH, r)
1212 opset(AVFENEF, r)
1213 opset(AVFENEBS, r)
1214 opset(AVFENEHS, r)
1215 opset(AVFENEFS, r)
1216 opset(AVFENEZB, r)
1217 opset(AVFENEZH, r)
1218 opset(AVFENEZF, r)
1219 opset(AVFENEZBS, r)
1220 opset(AVFENEZHS, r)
1221 opset(AVFENEZFS, r)
1222 case AVPKSG:
1223 opset(AVPKSH, r)
1224 opset(AVPKSF, r)
1225 opset(AVPKSHS, r)
1226 opset(AVPKSFS, r)
1227 opset(AVPKSGS, r)
1228 opset(AVPKLSH, r)
1229 opset(AVPKLSF, r)
1230 opset(AVPKLSG, r)
1231 opset(AVPKLSHS, r)
1232 opset(AVPKLSFS, r)
1233 opset(AVPKLSGS, r)
1234 case AVAQ:
1235 opset(AVAB, r)
1236 opset(AVAH, r)
1237 opset(AVAF, r)
1238 opset(AVAG, r)
1239 opset(AVACCB, r)
1240 opset(AVACCH, r)
1241 opset(AVACCF, r)
1242 opset(AVACCG, r)
1243 opset(AVACCQ, r)
1244 opset(AVN, r)
1245 opset(AVNC, r)
1246 opset(AVAVGB, r)
1247 opset(AVAVGH, r)
1248 opset(AVAVGF, r)
1249 opset(AVAVGG, r)
1250 opset(AVAVGLB, r)
1251 opset(AVAVGLH, r)
1252 opset(AVAVGLF, r)
1253 opset(AVAVGLG, r)
1254 opset(AVCKSM, r)
1255 opset(AVX, r)
1256 opset(AVFADB, r)
1257 opset(AWFADB, r)
1258 opset(AVFCEDB, r)
1259 opset(AVFCEDBS, r)
1260 opset(AWFCEDB, r)
1261 opset(AWFCEDBS, r)
1262 opset(AVFCHDB, r)
1263 opset(AVFCHDBS, r)
1264 opset(AWFCHDB, r)
1265 opset(AWFCHDBS, r)
1266 opset(AVFCHEDB, r)
1267 opset(AVFCHEDBS, r)
1268 opset(AWFCHEDB, r)
1269 opset(AWFCHEDBS, r)
1270 opset(AVFMDB, r)
1271 opset(AWFMDB, r)
1272 opset(AVGFMB, r)
1273 opset(AVGFMH, r)
1274 opset(AVGFMF, r)
1275 opset(AVGFMG, r)
1276 opset(AVMXB, r)
1277 opset(AVMXH, r)
1278 opset(AVMXF, r)
1279 opset(AVMXG, r)
1280 opset(AVMXLB, r)
1281 opset(AVMXLH, r)
1282 opset(AVMXLF, r)
1283 opset(AVMXLG, r)
1284 opset(AVMNB, r)
1285 opset(AVMNH, r)
1286 opset(AVMNF, r)
1287 opset(AVMNG, r)
1288 opset(AVMNLB, r)
1289 opset(AVMNLH, r)
1290 opset(AVMNLF, r)
1291 opset(AVMNLG, r)
1292 opset(AVMRHB, r)
1293 opset(AVMRHH, r)
1294 opset(AVMRHF, r)
1295 opset(AVMRHG, r)
1296 opset(AVMRLB, r)
1297 opset(AVMRLH, r)
1298 opset(AVMRLF, r)
1299 opset(AVMRLG, r)
1300 opset(AVMEB, r)
1301 opset(AVMEH, r)
1302 opset(AVMEF, r)
1303 opset(AVMLEB, r)
1304 opset(AVMLEH, r)
1305 opset(AVMLEF, r)
1306 opset(AVMOB, r)
1307 opset(AVMOH, r)
1308 opset(AVMOF, r)
1309 opset(AVMLOB, r)
1310 opset(AVMLOH, r)
1311 opset(AVMLOF, r)
1312 opset(AVMHB, r)
1313 opset(AVMHH, r)
1314 opset(AVMHF, r)
1315 opset(AVMLHB, r)
1316 opset(AVMLHH, r)
1317 opset(AVMLHF, r)
1318 opset(AVMLH, r)
1319 opset(AVMLHW, r)
1320 opset(AVMLF, r)
1321 opset(AVNO, r)
1322 opset(AVO, r)
1323 opset(AVPKH, r)
1324 opset(AVPKF, r)
1325 opset(AVPKG, r)
1326 opset(AVSUMGH, r)
1327 opset(AVSUMGF, r)
1328 opset(AVSUMQF, r)
1329 opset(AVSUMQG, r)
1330 opset(AVSUMB, r)
1331 opset(AVSUMH, r)
1332 case AVERLLVG:
1333 opset(AVERLLVB, r)
1334 opset(AVERLLVH, r)
1335 opset(AVERLLVF, r)
1336 opset(AVESLVB, r)
1337 opset(AVESLVH, r)
1338 opset(AVESLVF, r)
1339 opset(AVESLVG, r)
1340 opset(AVESRAVB, r)
1341 opset(AVESRAVH, r)
1342 opset(AVESRAVF, r)
1343 opset(AVESRAVG, r)
1344 opset(AVESRLVB, r)
1345 opset(AVESRLVH, r)
1346 opset(AVESRLVF, r)
1347 opset(AVESRLVG, r)
1348 opset(AVFDDB, r)
1349 opset(AWFDDB, r)
1350 opset(AVFSDB, r)
1351 opset(AWFSDB, r)
1352 opset(AVSL, r)
1353 opset(AVSLB, r)
1354 opset(AVSRA, r)
1355 opset(AVSRAB, r)
1356 opset(AVSRL, r)
1357 opset(AVSRLB, r)
1358 opset(AVSF, r)
1359 opset(AVSG, r)
1360 opset(AVSQ, r)
1361 opset(AVSCBIB, r)
1362 opset(AVSCBIH, r)
1363 opset(AVSCBIF, r)
1364 opset(AVSCBIG, r)
1365 opset(AVSCBIQ, r)
1366 case AVACQ:
1367 opset(AVACCCQ, r)
1368 opset(AVGFMAB, r)
1369 opset(AVGFMAH, r)
1370 opset(AVGFMAF, r)
1371 opset(AVGFMAG, r)
1372 opset(AVMALB, r)
1373 opset(AVMALHW, r)
1374 opset(AVMALF, r)
1375 opset(AVMAHB, r)
1376 opset(AVMAHH, r)
1377 opset(AVMAHF, r)
1378 opset(AVMALHB, r)
1379 opset(AVMALHH, r)
1380 opset(AVMALHF, r)
1381 opset(AVMAEB, r)
1382 opset(AVMAEH, r)
1383 opset(AVMAEF, r)
1384 opset(AVMALEB, r)
1385 opset(AVMALEH, r)
1386 opset(AVMALEF, r)
1387 opset(AVMAOB, r)
1388 opset(AVMAOH, r)
1389 opset(AVMAOF, r)
1390 opset(AVMALOB, r)
1391 opset(AVMALOH, r)
1392 opset(AVMALOF, r)
1393 opset(AVSTRCB, r)
1394 opset(AVSTRCH, r)
1395 opset(AVSTRCF, r)
1396 opset(AVSTRCBS, r)
1397 opset(AVSTRCHS, r)
1398 opset(AVSTRCFS, r)
1399 opset(AVSTRCZB, r)
1400 opset(AVSTRCZH, r)
1401 opset(AVSTRCZF, r)
1402 opset(AVSTRCZBS, r)
1403 opset(AVSTRCZHS, r)
1404 opset(AVSTRCZFS, r)
1405 opset(AVSBCBIQ, r)
1406 opset(AVSBIQ, r)
1407 opset(AVMSLG, r)
1408 opset(AVMSLEG, r)
1409 opset(AVMSLOG, r)
1410 opset(AVMSLEOG, r)
1411 case AVSEL:
1412 opset(AVFMADB, r)
1413 opset(AWFMADB, r)
1414 opset(AVFMSDB, r)
1415 opset(AWFMSDB, r)
1416 opset(AVPERM, r)
1417 }
1418 }
1419 }
1420
1421 const (
1422 op_A uint32 = 0x5A00
1423 op_AD uint32 = 0x6A00
1424 op_ADB uint32 = 0xED1A
1425 op_ADBR uint32 = 0xB31A
1426 op_ADR uint32 = 0x2A00
1427 op_ADTR uint32 = 0xB3D2
1428 op_ADTRA uint32 = 0xB3D2
1429 op_AE uint32 = 0x7A00
1430 op_AEB uint32 = 0xED0A
1431 op_AEBR uint32 = 0xB30A
1432 op_AER uint32 = 0x3A00
1433 op_AFI uint32 = 0xC209
1434 op_AG uint32 = 0xE308
1435 op_AGF uint32 = 0xE318
1436 op_AGFI uint32 = 0xC208
1437 op_AGFR uint32 = 0xB918
1438 op_AGHI uint32 = 0xA70B
1439 op_AGHIK uint32 = 0xECD9
1440 op_AGR uint32 = 0xB908
1441 op_AGRK uint32 = 0xB9E8
1442 op_AGSI uint32 = 0xEB7A
1443 op_AH uint32 = 0x4A00
1444 op_AHHHR uint32 = 0xB9C8
1445 op_AHHLR uint32 = 0xB9D8
1446 op_AHI uint32 = 0xA70A
1447 op_AHIK uint32 = 0xECD8
1448 op_AHY uint32 = 0xE37A
1449 op_AIH uint32 = 0xCC08
1450 op_AL uint32 = 0x5E00
1451 op_ALC uint32 = 0xE398
1452 op_ALCG uint32 = 0xE388
1453 op_ALCGR uint32 = 0xB988
1454 op_ALCR uint32 = 0xB998
1455 op_ALFI uint32 = 0xC20B
1456 op_ALG uint32 = 0xE30A
1457 op_ALGF uint32 = 0xE31A
1458 op_ALGFI uint32 = 0xC20A
1459 op_ALGFR uint32 = 0xB91A
1460 op_ALGHSIK uint32 = 0xECDB
1461 op_ALGR uint32 = 0xB90A
1462 op_ALGRK uint32 = 0xB9EA
1463 op_ALGSI uint32 = 0xEB7E
1464 op_ALHHHR uint32 = 0xB9CA
1465 op_ALHHLR uint32 = 0xB9DA
1466 op_ALHSIK uint32 = 0xECDA
1467 op_ALR uint32 = 0x1E00
1468 op_ALRK uint32 = 0xB9FA
1469 op_ALSI uint32 = 0xEB6E
1470 op_ALSIH uint32 = 0xCC0A
1471 op_ALSIHN uint32 = 0xCC0B
1472 op_ALY uint32 = 0xE35E
1473 op_AP uint32 = 0xFA00
1474 op_AR uint32 = 0x1A00
1475 op_ARK uint32 = 0xB9F8
1476 op_ASI uint32 = 0xEB6A
1477 op_AU uint32 = 0x7E00
1478 op_AUR uint32 = 0x3E00
1479 op_AW uint32 = 0x6E00
1480 op_AWR uint32 = 0x2E00
1481 op_AXBR uint32 = 0xB34A
1482 op_AXR uint32 = 0x3600
1483 op_AXTR uint32 = 0xB3DA
1484 op_AXTRA uint32 = 0xB3DA
1485 op_AY uint32 = 0xE35A
1486 op_BAKR uint32 = 0xB240
1487 op_BAL uint32 = 0x4500
1488 op_BALR uint32 = 0x0500
1489 op_BAS uint32 = 0x4D00
1490 op_BASR uint32 = 0x0D00
1491 op_BASSM uint32 = 0x0C00
1492 op_BC uint32 = 0x4700
1493 op_BCR uint32 = 0x0700
1494 op_BCT uint32 = 0x4600
1495 op_BCTG uint32 = 0xE346
1496 op_BCTGR uint32 = 0xB946
1497 op_BCTR uint32 = 0x0600
1498 op_BPP uint32 = 0xC700
1499 op_BPRP uint32 = 0xC500
1500 op_BRAS uint32 = 0xA705
1501 op_BRASL uint32 = 0xC005
1502 op_BRC uint32 = 0xA704
1503 op_BRCL uint32 = 0xC004
1504 op_BRCT uint32 = 0xA706
1505 op_BRCTG uint32 = 0xA707
1506 op_BRCTH uint32 = 0xCC06
1507 op_BRXH uint32 = 0x8400
1508 op_BRXHG uint32 = 0xEC44
1509 op_BRXLE uint32 = 0x8500
1510 op_BRXLG uint32 = 0xEC45
1511 op_BSA uint32 = 0xB25A
1512 op_BSG uint32 = 0xB258
1513 op_BSM uint32 = 0x0B00
1514 op_BXH uint32 = 0x8600
1515 op_BXHG uint32 = 0xEB44
1516 op_BXLE uint32 = 0x8700
1517 op_BXLEG uint32 = 0xEB45
1518 op_C uint32 = 0x5900
1519 op_CD uint32 = 0x6900
1520 op_CDB uint32 = 0xED19
1521 op_CDBR uint32 = 0xB319
1522 op_CDFBR uint32 = 0xB395
1523 op_CDFBRA uint32 = 0xB395
1524 op_CDFR uint32 = 0xB3B5
1525 op_CDFTR uint32 = 0xB951
1526 op_CDGBR uint32 = 0xB3A5
1527 op_CDGBRA uint32 = 0xB3A5
1528 op_CDGR uint32 = 0xB3C5
1529 op_CDGTR uint32 = 0xB3F1
1530 op_CDGTRA uint32 = 0xB3F1
1531 op_CDLFBR uint32 = 0xB391
1532 op_CDLFTR uint32 = 0xB953
1533 op_CDLGBR uint32 = 0xB3A1
1534 op_CDLGTR uint32 = 0xB952
1535 op_CDR uint32 = 0x2900
1536 op_CDS uint32 = 0xBB00
1537 op_CDSG uint32 = 0xEB3E
1538 op_CDSTR uint32 = 0xB3F3
1539 op_CDSY uint32 = 0xEB31
1540 op_CDTR uint32 = 0xB3E4
1541 op_CDUTR uint32 = 0xB3F2
1542 op_CDZT uint32 = 0xEDAA
1543 op_CE uint32 = 0x7900
1544 op_CEB uint32 = 0xED09
1545 op_CEBR uint32 = 0xB309
1546 op_CEDTR uint32 = 0xB3F4
1547 op_CEFBR uint32 = 0xB394
1548 op_CEFBRA uint32 = 0xB394
1549 op_CEFR uint32 = 0xB3B4
1550 op_CEGBR uint32 = 0xB3A4
1551 op_CEGBRA uint32 = 0xB3A4
1552 op_CEGR uint32 = 0xB3C4
1553 op_CELFBR uint32 = 0xB390
1554 op_CELGBR uint32 = 0xB3A0
1555 op_CER uint32 = 0x3900
1556 op_CEXTR uint32 = 0xB3FC
1557 op_CFC uint32 = 0xB21A
1558 op_CFDBR uint32 = 0xB399
1559 op_CFDBRA uint32 = 0xB399
1560 op_CFDR uint32 = 0xB3B9
1561 op_CFDTR uint32 = 0xB941
1562 op_CFEBR uint32 = 0xB398
1563 op_CFEBRA uint32 = 0xB398
1564 op_CFER uint32 = 0xB3B8
1565 op_CFI uint32 = 0xC20D
1566 op_CFXBR uint32 = 0xB39A
1567 op_CFXBRA uint32 = 0xB39A
1568 op_CFXR uint32 = 0xB3BA
1569 op_CFXTR uint32 = 0xB949
1570 op_CG uint32 = 0xE320
1571 op_CGDBR uint32 = 0xB3A9
1572 op_CGDBRA uint32 = 0xB3A9
1573 op_CGDR uint32 = 0xB3C9
1574 op_CGDTR uint32 = 0xB3E1
1575 op_CGDTRA uint32 = 0xB3E1
1576 op_CGEBR uint32 = 0xB3A8
1577 op_CGEBRA uint32 = 0xB3A8
1578 op_CGER uint32 = 0xB3C8
1579 op_CGF uint32 = 0xE330
1580 op_CGFI uint32 = 0xC20C
1581 op_CGFR uint32 = 0xB930
1582 op_CGFRL uint32 = 0xC60C
1583 op_CGH uint32 = 0xE334
1584 op_CGHI uint32 = 0xA70F
1585 op_CGHRL uint32 = 0xC604
1586 op_CGHSI uint32 = 0xE558
1587 op_CGIB uint32 = 0xECFC
1588 op_CGIJ uint32 = 0xEC7C
1589 op_CGIT uint32 = 0xEC70
1590 op_CGR uint32 = 0xB920
1591 op_CGRB uint32 = 0xECE4
1592 op_CGRJ uint32 = 0xEC64
1593 op_CGRL uint32 = 0xC608
1594 op_CGRT uint32 = 0xB960
1595 op_CGXBR uint32 = 0xB3AA
1596 op_CGXBRA uint32 = 0xB3AA
1597 op_CGXR uint32 = 0xB3CA
1598 op_CGXTR uint32 = 0xB3E9
1599 op_CGXTRA uint32 = 0xB3E9
1600 op_CH uint32 = 0x4900
1601 op_CHF uint32 = 0xE3CD
1602 op_CHHR uint32 = 0xB9CD
1603 op_CHHSI uint32 = 0xE554
1604 op_CHI uint32 = 0xA70E
1605 op_CHLR uint32 = 0xB9DD
1606 op_CHRL uint32 = 0xC605
1607 op_CHSI uint32 = 0xE55C
1608 op_CHY uint32 = 0xE379
1609 op_CIB uint32 = 0xECFE
1610 op_CIH uint32 = 0xCC0D
1611 op_CIJ uint32 = 0xEC7E
1612 op_CIT uint32 = 0xEC72
1613 op_CKSM uint32 = 0xB241
1614 op_CL uint32 = 0x5500
1615 op_CLC uint32 = 0xD500
1616 op_CLCL uint32 = 0x0F00
1617 op_CLCLE uint32 = 0xA900
1618 op_CLCLU uint32 = 0xEB8F
1619 op_CLFDBR uint32 = 0xB39D
1620 op_CLFDTR uint32 = 0xB943
1621 op_CLFEBR uint32 = 0xB39C
1622 op_CLFHSI uint32 = 0xE55D
1623 op_CLFI uint32 = 0xC20F
1624 op_CLFIT uint32 = 0xEC73
1625 op_CLFXBR uint32 = 0xB39E
1626 op_CLFXTR uint32 = 0xB94B
1627 op_CLG uint32 = 0xE321
1628 op_CLGDBR uint32 = 0xB3AD
1629 op_CLGDTR uint32 = 0xB942
1630 op_CLGEBR uint32 = 0xB3AC
1631 op_CLGF uint32 = 0xE331
1632 op_CLGFI uint32 = 0xC20E
1633 op_CLGFR uint32 = 0xB931
1634 op_CLGFRL uint32 = 0xC60E
1635 op_CLGHRL uint32 = 0xC606
1636 op_CLGHSI uint32 = 0xE559
1637 op_CLGIB uint32 = 0xECFD
1638 op_CLGIJ uint32 = 0xEC7D
1639 op_CLGIT uint32 = 0xEC71
1640 op_CLGR uint32 = 0xB921
1641 op_CLGRB uint32 = 0xECE5
1642 op_CLGRJ uint32 = 0xEC65
1643 op_CLGRL uint32 = 0xC60A
1644 op_CLGRT uint32 = 0xB961
1645 op_CLGT uint32 = 0xEB2B
1646 op_CLGXBR uint32 = 0xB3AE
1647 op_CLGXTR uint32 = 0xB94A
1648 op_CLHF uint32 = 0xE3CF
1649 op_CLHHR uint32 = 0xB9CF
1650 op_CLHHSI uint32 = 0xE555
1651 op_CLHLR uint32 = 0xB9DF
1652 op_CLHRL uint32 = 0xC607
1653 op_CLI uint32 = 0x9500
1654 op_CLIB uint32 = 0xECFF
1655 op_CLIH uint32 = 0xCC0F
1656 op_CLIJ uint32 = 0xEC7F
1657 op_CLIY uint32 = 0xEB55
1658 op_CLM uint32 = 0xBD00
1659 op_CLMH uint32 = 0xEB20
1660 op_CLMY uint32 = 0xEB21
1661 op_CLR uint32 = 0x1500
1662 op_CLRB uint32 = 0xECF7
1663 op_CLRJ uint32 = 0xEC77
1664 op_CLRL uint32 = 0xC60F
1665 op_CLRT uint32 = 0xB973
1666 op_CLST uint32 = 0xB25D
1667 op_CLT uint32 = 0xEB23
1668 op_CLY uint32 = 0xE355
1669 op_CMPSC uint32 = 0xB263
1670 op_CP uint32 = 0xF900
1671 op_CPSDR uint32 = 0xB372
1672 op_CPYA uint32 = 0xB24D
1673 op_CR uint32 = 0x1900
1674 op_CRB uint32 = 0xECF6
1675 op_CRDTE uint32 = 0xB98F
1676 op_CRJ uint32 = 0xEC76
1677 op_CRL uint32 = 0xC60D
1678 op_CRT uint32 = 0xB972
1679 op_CS uint32 = 0xBA00
1680 op_CSCH uint32 = 0xB230
1681 op_CSDTR uint32 = 0xB3E3
1682 op_CSG uint32 = 0xEB30
1683 op_CSP uint32 = 0xB250
1684 op_CSPG uint32 = 0xB98A
1685 op_CSST uint32 = 0xC802
1686 op_CSXTR uint32 = 0xB3EB
1687 op_CSY uint32 = 0xEB14
1688 op_CU12 uint32 = 0xB2A7
1689 op_CU14 uint32 = 0xB9B0
1690 op_CU21 uint32 = 0xB2A6
1691 op_CU24 uint32 = 0xB9B1
1692 op_CU41 uint32 = 0xB9B2
1693 op_CU42 uint32 = 0xB9B3
1694 op_CUDTR uint32 = 0xB3E2
1695 op_CUSE uint32 = 0xB257
1696 op_CUTFU uint32 = 0xB2A7
1697 op_CUUTF uint32 = 0xB2A6
1698 op_CUXTR uint32 = 0xB3EA
1699 op_CVB uint32 = 0x4F00
1700 op_CVBG uint32 = 0xE30E
1701 op_CVBY uint32 = 0xE306
1702 op_CVD uint32 = 0x4E00
1703 op_CVDG uint32 = 0xE32E
1704 op_CVDY uint32 = 0xE326
1705 op_CXBR uint32 = 0xB349
1706 op_CXFBR uint32 = 0xB396
1707 op_CXFBRA uint32 = 0xB396
1708 op_CXFR uint32 = 0xB3B6
1709 op_CXFTR uint32 = 0xB959
1710 op_CXGBR uint32 = 0xB3A6
1711 op_CXGBRA uint32 = 0xB3A6
1712 op_CXGR uint32 = 0xB3C6
1713 op_CXGTR uint32 = 0xB3F9
1714 op_CXGTRA uint32 = 0xB3F9
1715 op_CXLFBR uint32 = 0xB392
1716 op_CXLFTR uint32 = 0xB95B
1717 op_CXLGBR uint32 = 0xB3A2
1718 op_CXLGTR uint32 = 0xB95A
1719 op_CXR uint32 = 0xB369
1720 op_CXSTR uint32 = 0xB3FB
1721 op_CXTR uint32 = 0xB3EC
1722 op_CXUTR uint32 = 0xB3FA
1723 op_CXZT uint32 = 0xEDAB
1724 op_CY uint32 = 0xE359
1725 op_CZDT uint32 = 0xEDA8
1726 op_CZXT uint32 = 0xEDA9
1727 op_D uint32 = 0x5D00
1728 op_DD uint32 = 0x6D00
1729 op_DDB uint32 = 0xED1D
1730 op_DDBR uint32 = 0xB31D
1731 op_DDR uint32 = 0x2D00
1732 op_DDTR uint32 = 0xB3D1
1733 op_DDTRA uint32 = 0xB3D1
1734 op_DE uint32 = 0x7D00
1735 op_DEB uint32 = 0xED0D
1736 op_DEBR uint32 = 0xB30D
1737 op_DER uint32 = 0x3D00
1738 op_DIDBR uint32 = 0xB35B
1739 op_DIEBR uint32 = 0xB353
1740 op_DL uint32 = 0xE397
1741 op_DLG uint32 = 0xE387
1742 op_DLGR uint32 = 0xB987
1743 op_DLR uint32 = 0xB997
1744 op_DP uint32 = 0xFD00
1745 op_DR uint32 = 0x1D00
1746 op_DSG uint32 = 0xE30D
1747 op_DSGF uint32 = 0xE31D
1748 op_DSGFR uint32 = 0xB91D
1749 op_DSGR uint32 = 0xB90D
1750 op_DXBR uint32 = 0xB34D
1751 op_DXR uint32 = 0xB22D
1752 op_DXTR uint32 = 0xB3D9
1753 op_DXTRA uint32 = 0xB3D9
1754 op_EAR uint32 = 0xB24F
1755 op_ECAG uint32 = 0xEB4C
1756 op_ECTG uint32 = 0xC801
1757 op_ED uint32 = 0xDE00
1758 op_EDMK uint32 = 0xDF00
1759 op_EEDTR uint32 = 0xB3E5
1760 op_EEXTR uint32 = 0xB3ED
1761 op_EFPC uint32 = 0xB38C
1762 op_EPAIR uint32 = 0xB99A
1763 op_EPAR uint32 = 0xB226
1764 op_EPSW uint32 = 0xB98D
1765 op_EREG uint32 = 0xB249
1766 op_EREGG uint32 = 0xB90E
1767 op_ESAIR uint32 = 0xB99B
1768 op_ESAR uint32 = 0xB227
1769 op_ESDTR uint32 = 0xB3E7
1770 op_ESEA uint32 = 0xB99D
1771 op_ESTA uint32 = 0xB24A
1772 op_ESXTR uint32 = 0xB3EF
1773 op_ETND uint32 = 0xB2EC
1774 op_EX uint32 = 0x4400
1775 op_EXRL uint32 = 0xC600
1776 op_FIDBR uint32 = 0xB35F
1777 op_FIDBRA uint32 = 0xB35F
1778 op_FIDR uint32 = 0xB37F
1779 op_FIDTR uint32 = 0xB3D7
1780 op_FIEBR uint32 = 0xB357
1781 op_FIEBRA uint32 = 0xB357
1782 op_FIER uint32 = 0xB377
1783 op_FIXBR uint32 = 0xB347
1784 op_FIXBRA uint32 = 0xB347
1785 op_FIXR uint32 = 0xB367
1786 op_FIXTR uint32 = 0xB3DF
1787 op_FLOGR uint32 = 0xB983
1788 op_HDR uint32 = 0x2400
1789 op_HER uint32 = 0x3400
1790 op_HSCH uint32 = 0xB231
1791 op_IAC uint32 = 0xB224
1792 op_IC uint32 = 0x4300
1793 op_ICM uint32 = 0xBF00
1794 op_ICMH uint32 = 0xEB80
1795 op_ICMY uint32 = 0xEB81
1796 op_ICY uint32 = 0xE373
1797 op_IDTE uint32 = 0xB98E
1798 op_IEDTR uint32 = 0xB3F6
1799 op_IEXTR uint32 = 0xB3FE
1800 op_IIHF uint32 = 0xC008
1801 op_IIHH uint32 = 0xA500
1802 op_IIHL uint32 = 0xA501
1803 op_IILF uint32 = 0xC009
1804 op_IILH uint32 = 0xA502
1805 op_IILL uint32 = 0xA503
1806 op_IPK uint32 = 0xB20B
1807 op_IPM uint32 = 0xB222
1808 op_IPTE uint32 = 0xB221
1809 op_ISKE uint32 = 0xB229
1810 op_IVSK uint32 = 0xB223
1811 op_KDB uint32 = 0xED18
1812 op_KDBR uint32 = 0xB318
1813 op_KDTR uint32 = 0xB3E0
1814 op_KEB uint32 = 0xED08
1815 op_KEBR uint32 = 0xB308
1816 op_KIMD uint32 = 0xB93E
1817 op_KLMD uint32 = 0xB93F
1818 op_KM uint32 = 0xB92E
1819 op_KMAC uint32 = 0xB91E
1820 op_KMC uint32 = 0xB92F
1821 op_KMCTR uint32 = 0xB92D
1822 op_KMF uint32 = 0xB92A
1823 op_KMO uint32 = 0xB92B
1824 op_KXBR uint32 = 0xB348
1825 op_KXTR uint32 = 0xB3E8
1826 op_L uint32 = 0x5800
1827 op_LA uint32 = 0x4100
1828 op_LAA uint32 = 0xEBF8
1829 op_LAAG uint32 = 0xEBE8
1830 op_LAAL uint32 = 0xEBFA
1831 op_LAALG uint32 = 0xEBEA
1832 op_LAE uint32 = 0x5100
1833 op_LAEY uint32 = 0xE375
1834 op_LAM uint32 = 0x9A00
1835 op_LAMY uint32 = 0xEB9A
1836 op_LAN uint32 = 0xEBF4
1837 op_LANG uint32 = 0xEBE4
1838 op_LAO uint32 = 0xEBF6
1839 op_LAOG uint32 = 0xEBE6
1840 op_LARL uint32 = 0xC000
1841 op_LASP uint32 = 0xE500
1842 op_LAT uint32 = 0xE39F
1843 op_LAX uint32 = 0xEBF7
1844 op_LAXG uint32 = 0xEBE7
1845 op_LAY uint32 = 0xE371
1846 op_LB uint32 = 0xE376
1847 op_LBH uint32 = 0xE3C0
1848 op_LBR uint32 = 0xB926
1849 op_LCDBR uint32 = 0xB313
1850 op_LCDFR uint32 = 0xB373
1851 op_LCDR uint32 = 0x2300
1852 op_LCEBR uint32 = 0xB303
1853 op_LCER uint32 = 0x3300
1854 op_LCGFR uint32 = 0xB913
1855 op_LCGR uint32 = 0xB903
1856 op_LCR uint32 = 0x1300
1857 op_LCTL uint32 = 0xB700
1858 op_LCTLG uint32 = 0xEB2F
1859 op_LCXBR uint32 = 0xB343
1860 op_LCXR uint32 = 0xB363
1861 op_LD uint32 = 0x6800
1862 op_LDE uint32 = 0xED24
1863 op_LDEB uint32 = 0xED04
1864 op_LDEBR uint32 = 0xB304
1865 op_LDER uint32 = 0xB324
1866 op_LDETR uint32 = 0xB3D4
1867 op_LDGR uint32 = 0xB3C1
1868 op_LDR uint32 = 0x2800
1869 op_LDXBR uint32 = 0xB345
1870 op_LDXBRA uint32 = 0xB345
1871 op_LDXR uint32 = 0x2500
1872 op_LDXTR uint32 = 0xB3DD
1873 op_LDY uint32 = 0xED65
1874 op_LE uint32 = 0x7800
1875 op_LEDBR uint32 = 0xB344
1876 op_LEDBRA uint32 = 0xB344
1877 op_LEDR uint32 = 0x3500
1878 op_LEDTR uint32 = 0xB3D5
1879 op_LER uint32 = 0x3800
1880 op_LEXBR uint32 = 0xB346
1881 op_LEXBRA uint32 = 0xB346
1882 op_LEXR uint32 = 0xB366
1883 op_LEY uint32 = 0xED64
1884 op_LFAS uint32 = 0xB2BD
1885 op_LFH uint32 = 0xE3CA
1886 op_LFHAT uint32 = 0xE3C8
1887 op_LFPC uint32 = 0xB29D
1888 op_LG uint32 = 0xE304
1889 op_LGAT uint32 = 0xE385
1890 op_LGB uint32 = 0xE377
1891 op_LGBR uint32 = 0xB906
1892 op_LGDR uint32 = 0xB3CD
1893 op_LGF uint32 = 0xE314
1894 op_LGFI uint32 = 0xC001
1895 op_LGFR uint32 = 0xB914
1896 op_LGFRL uint32 = 0xC40C
1897 op_LGH uint32 = 0xE315
1898 op_LGHI uint32 = 0xA709
1899 op_LGHR uint32 = 0xB907
1900 op_LGHRL uint32 = 0xC404
1901 op_LGR uint32 = 0xB904
1902 op_LGRL uint32 = 0xC408
1903 op_LH uint32 = 0x4800
1904 op_LHH uint32 = 0xE3C4
1905 op_LHI uint32 = 0xA708
1906 op_LHR uint32 = 0xB927
1907 op_LHRL uint32 = 0xC405
1908 op_LHY uint32 = 0xE378
1909 op_LLC uint32 = 0xE394
1910 op_LLCH uint32 = 0xE3C2
1911 op_LLCR uint32 = 0xB994
1912 op_LLGC uint32 = 0xE390
1913 op_LLGCR uint32 = 0xB984
1914 op_LLGF uint32 = 0xE316
1915 op_LLGFAT uint32 = 0xE39D
1916 op_LLGFR uint32 = 0xB916
1917 op_LLGFRL uint32 = 0xC40E
1918 op_LLGH uint32 = 0xE391
1919 op_LLGHR uint32 = 0xB985
1920 op_LLGHRL uint32 = 0xC406
1921 op_LLGT uint32 = 0xE317
1922 op_LLGTAT uint32 = 0xE39C
1923 op_LLGTR uint32 = 0xB917
1924 op_LLH uint32 = 0xE395
1925 op_LLHH uint32 = 0xE3C6
1926 op_LLHR uint32 = 0xB995
1927 op_LLHRL uint32 = 0xC402
1928 op_LLIHF uint32 = 0xC00E
1929 op_LLIHH uint32 = 0xA50C
1930 op_LLIHL uint32 = 0xA50D
1931 op_LLILF uint32 = 0xC00F
1932 op_LLILH uint32 = 0xA50E
1933 op_LLILL uint32 = 0xA50F
1934 op_LM uint32 = 0x9800
1935 op_LMD uint32 = 0xEF00
1936 op_LMG uint32 = 0xEB04
1937 op_LMH uint32 = 0xEB96
1938 op_LMY uint32 = 0xEB98
1939 op_LNDBR uint32 = 0xB311
1940 op_LNDFR uint32 = 0xB371
1941 op_LNDR uint32 = 0x2100
1942 op_LNEBR uint32 = 0xB301
1943 op_LNER uint32 = 0x3100
1944 op_LNGFR uint32 = 0xB911
1945 op_LNGR uint32 = 0xB901
1946 op_LNR uint32 = 0x1100
1947 op_LNXBR uint32 = 0xB341
1948 op_LNXR uint32 = 0xB361
1949 op_LOC uint32 = 0xEBF2
1950 op_LOCG uint32 = 0xEBE2
1951 op_LOCGR uint32 = 0xB9E2
1952 op_LOCR uint32 = 0xB9F2
1953 op_LPD uint32 = 0xC804
1954 op_LPDBR uint32 = 0xB310
1955 op_LPDFR uint32 = 0xB370
1956 op_LPDG uint32 = 0xC805
1957 op_LPDR uint32 = 0x2000
1958 op_LPEBR uint32 = 0xB300
1959 op_LPER uint32 = 0x3000
1960 op_LPGFR uint32 = 0xB910
1961 op_LPGR uint32 = 0xB900
1962 op_LPQ uint32 = 0xE38F
1963 op_LPR uint32 = 0x1000
1964 op_LPSW uint32 = 0x8200
1965 op_LPSWE uint32 = 0xB2B2
1966 op_LPTEA uint32 = 0xB9AA
1967 op_LPXBR uint32 = 0xB340
1968 op_LPXR uint32 = 0xB360
1969 op_LR uint32 = 0x1800
1970 op_LRA uint32 = 0xB100
1971 op_LRAG uint32 = 0xE303
1972 op_LRAY uint32 = 0xE313
1973 op_LRDR uint32 = 0x2500
1974 op_LRER uint32 = 0x3500
1975 op_LRL uint32 = 0xC40D
1976 op_LRV uint32 = 0xE31E
1977 op_LRVG uint32 = 0xE30F
1978 op_LRVGR uint32 = 0xB90F
1979 op_LRVH uint32 = 0xE31F
1980 op_LRVR uint32 = 0xB91F
1981 op_LT uint32 = 0xE312
1982 op_LTDBR uint32 = 0xB312
1983 op_LTDR uint32 = 0x2200
1984 op_LTDTR uint32 = 0xB3D6
1985 op_LTEBR uint32 = 0xB302
1986 op_LTER uint32 = 0x3200
1987 op_LTG uint32 = 0xE302
1988 op_LTGF uint32 = 0xE332
1989 op_LTGFR uint32 = 0xB912
1990 op_LTGR uint32 = 0xB902
1991 op_LTR uint32 = 0x1200
1992 op_LTXBR uint32 = 0xB342
1993 op_LTXR uint32 = 0xB362
1994 op_LTXTR uint32 = 0xB3DE
1995 op_LURA uint32 = 0xB24B
1996 op_LURAG uint32 = 0xB905
1997 op_LXD uint32 = 0xED25
1998 op_LXDB uint32 = 0xED05
1999 op_LXDBR uint32 = 0xB305
2000 op_LXDR uint32 = 0xB325
2001 op_LXDTR uint32 = 0xB3DC
2002 op_LXE uint32 = 0xED26
2003 op_LXEB uint32 = 0xED06
2004 op_LXEBR uint32 = 0xB306
2005 op_LXER uint32 = 0xB326
2006 op_LXR uint32 = 0xB365
2007 op_LY uint32 = 0xE358
2008 op_LZDR uint32 = 0xB375
2009 op_LZER uint32 = 0xB374
2010 op_LZXR uint32 = 0xB376
2011 op_M uint32 = 0x5C00
2012 op_MAD uint32 = 0xED3E
2013 op_MADB uint32 = 0xED1E
2014 op_MADBR uint32 = 0xB31E
2015 op_MADR uint32 = 0xB33E
2016 op_MAE uint32 = 0xED2E
2017 op_MAEB uint32 = 0xED0E
2018 op_MAEBR uint32 = 0xB30E
2019 op_MAER uint32 = 0xB32E
2020 op_MAY uint32 = 0xED3A
2021 op_MAYH uint32 = 0xED3C
2022 op_MAYHR uint32 = 0xB33C
2023 op_MAYL uint32 = 0xED38
2024 op_MAYLR uint32 = 0xB338
2025 op_MAYR uint32 = 0xB33A
2026 op_MC uint32 = 0xAF00
2027 op_MD uint32 = 0x6C00
2028 op_MDB uint32 = 0xED1C
2029 op_MDBR uint32 = 0xB31C
2030 op_MDE uint32 = 0x7C00
2031 op_MDEB uint32 = 0xED0C
2032 op_MDEBR uint32 = 0xB30C
2033 op_MDER uint32 = 0x3C00
2034 op_MDR uint32 = 0x2C00
2035 op_MDTR uint32 = 0xB3D0
2036 op_MDTRA uint32 = 0xB3D0
2037 op_ME uint32 = 0x7C00
2038 op_MEE uint32 = 0xED37
2039 op_MEEB uint32 = 0xED17
2040 op_MEEBR uint32 = 0xB317
2041 op_MEER uint32 = 0xB337
2042 op_MER uint32 = 0x3C00
2043 op_MFY uint32 = 0xE35C
2044 op_MGHI uint32 = 0xA70D
2045 op_MH uint32 = 0x4C00
2046 op_MHI uint32 = 0xA70C
2047 op_MHY uint32 = 0xE37C
2048 op_ML uint32 = 0xE396
2049 op_MLG uint32 = 0xE386
2050 op_MLGR uint32 = 0xB986
2051 op_MLR uint32 = 0xB996
2052 op_MP uint32 = 0xFC00
2053 op_MR uint32 = 0x1C00
2054 op_MS uint32 = 0x7100
2055 op_MSCH uint32 = 0xB232
2056 op_MSD uint32 = 0xED3F
2057 op_MSDB uint32 = 0xED1F
2058 op_MSDBR uint32 = 0xB31F
2059 op_MSDR uint32 = 0xB33F
2060 op_MSE uint32 = 0xED2F
2061 op_MSEB uint32 = 0xED0F
2062 op_MSEBR uint32 = 0xB30F
2063 op_MSER uint32 = 0xB32F
2064 op_MSFI uint32 = 0xC201
2065 op_MSG uint32 = 0xE30C
2066 op_MSGF uint32 = 0xE31C
2067 op_MSGFI uint32 = 0xC200
2068 op_MSGFR uint32 = 0xB91C
2069 op_MSGR uint32 = 0xB90C
2070 op_MSR uint32 = 0xB252
2071 op_MSTA uint32 = 0xB247
2072 op_MSY uint32 = 0xE351
2073 op_MVC uint32 = 0xD200
2074 op_MVCDK uint32 = 0xE50F
2075 op_MVCIN uint32 = 0xE800
2076 op_MVCK uint32 = 0xD900
2077 op_MVCL uint32 = 0x0E00
2078 op_MVCLE uint32 = 0xA800
2079 op_MVCLU uint32 = 0xEB8E
2080 op_MVCOS uint32 = 0xC800
2081 op_MVCP uint32 = 0xDA00
2082 op_MVCS uint32 = 0xDB00
2083 op_MVCSK uint32 = 0xE50E
2084 op_MVGHI uint32 = 0xE548
2085 op_MVHHI uint32 = 0xE544
2086 op_MVHI uint32 = 0xE54C
2087 op_MVI uint32 = 0x9200
2088 op_MVIY uint32 = 0xEB52
2089 op_MVN uint32 = 0xD100
2090 op_MVO uint32 = 0xF100
2091 op_MVPG uint32 = 0xB254
2092 op_MVST uint32 = 0xB255
2093 op_MVZ uint32 = 0xD300
2094 op_MXBR uint32 = 0xB34C
2095 op_MXD uint32 = 0x6700
2096 op_MXDB uint32 = 0xED07
2097 op_MXDBR uint32 = 0xB307
2098 op_MXDR uint32 = 0x2700
2099 op_MXR uint32 = 0x2600
2100 op_MXTR uint32 = 0xB3D8
2101 op_MXTRA uint32 = 0xB3D8
2102 op_MY uint32 = 0xED3B
2103 op_MYH uint32 = 0xED3D
2104 op_MYHR uint32 = 0xB33D
2105 op_MYL uint32 = 0xED39
2106 op_MYLR uint32 = 0xB339
2107 op_MYR uint32 = 0xB33B
2108 op_N uint32 = 0x5400
2109 op_NC uint32 = 0xD400
2110 op_NG uint32 = 0xE380
2111 op_NGR uint32 = 0xB980
2112 op_NGRK uint32 = 0xB9E4
2113 op_NI uint32 = 0x9400
2114 op_NIAI uint32 = 0xB2FA
2115 op_NIHF uint32 = 0xC00A
2116 op_NIHH uint32 = 0xA504
2117 op_NIHL uint32 = 0xA505
2118 op_NILF uint32 = 0xC00B
2119 op_NILH uint32 = 0xA506
2120 op_NILL uint32 = 0xA507
2121 op_NIY uint32 = 0xEB54
2122 op_NR uint32 = 0x1400
2123 op_NRK uint32 = 0xB9F4
2124 op_NTSTG uint32 = 0xE325
2125 op_NY uint32 = 0xE354
2126 op_O uint32 = 0x5600
2127 op_OC uint32 = 0xD600
2128 op_OG uint32 = 0xE381
2129 op_OGR uint32 = 0xB981
2130 op_OGRK uint32 = 0xB9E6
2131 op_OI uint32 = 0x9600
2132 op_OIHF uint32 = 0xC00C
2133 op_OIHH uint32 = 0xA508
2134 op_OIHL uint32 = 0xA509
2135 op_OILF uint32 = 0xC00D
2136 op_OILH uint32 = 0xA50A
2137 op_OILL uint32 = 0xA50B
2138 op_OIY uint32 = 0xEB56
2139 op_OR uint32 = 0x1600
2140 op_ORK uint32 = 0xB9F6
2141 op_OY uint32 = 0xE356
2142 op_PACK uint32 = 0xF200
2143 op_PALB uint32 = 0xB248
2144 op_PC uint32 = 0xB218
2145 op_PCC uint32 = 0xB92C
2146 op_PCKMO uint32 = 0xB928
2147 op_PFD uint32 = 0xE336
2148 op_PFDRL uint32 = 0xC602
2149 op_PFMF uint32 = 0xB9AF
2150 op_PFPO uint32 = 0x010A
2151 op_PGIN uint32 = 0xB22E
2152 op_PGOUT uint32 = 0xB22F
2153 op_PKA uint32 = 0xE900
2154 op_PKU uint32 = 0xE100
2155 op_PLO uint32 = 0xEE00
2156 op_POPCNT uint32 = 0xB9E1
2157 op_PPA uint32 = 0xB2E8
2158 op_PR uint32 = 0x0101
2159 op_PT uint32 = 0xB228
2160 op_PTF uint32 = 0xB9A2
2161 op_PTFF uint32 = 0x0104
2162 op_PTI uint32 = 0xB99E
2163 op_PTLB uint32 = 0xB20D
2164 op_QADTR uint32 = 0xB3F5
2165 op_QAXTR uint32 = 0xB3FD
2166 op_RCHP uint32 = 0xB23B
2167 op_RISBG uint32 = 0xEC55
2168 op_RISBGN uint32 = 0xEC59
2169 op_RISBHG uint32 = 0xEC5D
2170 op_RISBLG uint32 = 0xEC51
2171 op_RLL uint32 = 0xEB1D
2172 op_RLLG uint32 = 0xEB1C
2173 op_RNSBG uint32 = 0xEC54
2174 op_ROSBG uint32 = 0xEC56
2175 op_RP uint32 = 0xB277
2176 op_RRBE uint32 = 0xB22A
2177 op_RRBM uint32 = 0xB9AE
2178 op_RRDTR uint32 = 0xB3F7
2179 op_RRXTR uint32 = 0xB3FF
2180 op_RSCH uint32 = 0xB238
2181 op_RXSBG uint32 = 0xEC57
2182 op_S uint32 = 0x5B00
2183 op_SAC uint32 = 0xB219
2184 op_SACF uint32 = 0xB279
2185 op_SAL uint32 = 0xB237
2186 op_SAM24 uint32 = 0x010C
2187 op_SAM31 uint32 = 0x010D
2188 op_SAM64 uint32 = 0x010E
2189 op_SAR uint32 = 0xB24E
2190 op_SCHM uint32 = 0xB23C
2191 op_SCK uint32 = 0xB204
2192 op_SCKC uint32 = 0xB206
2193 op_SCKPF uint32 = 0x0107
2194 op_SD uint32 = 0x6B00
2195 op_SDB uint32 = 0xED1B
2196 op_SDBR uint32 = 0xB31B
2197 op_SDR uint32 = 0x2B00
2198 op_SDTR uint32 = 0xB3D3
2199 op_SDTRA uint32 = 0xB3D3
2200 op_SE uint32 = 0x7B00
2201 op_SEB uint32 = 0xED0B
2202 op_SEBR uint32 = 0xB30B
2203 op_SER uint32 = 0x3B00
2204 op_SFASR uint32 = 0xB385
2205 op_SFPC uint32 = 0xB384
2206 op_SG uint32 = 0xE309
2207 op_SGF uint32 = 0xE319
2208 op_SGFR uint32 = 0xB919
2209 op_SGR uint32 = 0xB909
2210 op_SGRK uint32 = 0xB9E9
2211 op_SH uint32 = 0x4B00
2212 op_SHHHR uint32 = 0xB9C9
2213 op_SHHLR uint32 = 0xB9D9
2214 op_SHY uint32 = 0xE37B
2215 op_SIGP uint32 = 0xAE00
2216 op_SL uint32 = 0x5F00
2217 op_SLA uint32 = 0x8B00
2218 op_SLAG uint32 = 0xEB0B
2219 op_SLAK uint32 = 0xEBDD
2220 op_SLB uint32 = 0xE399
2221 op_SLBG uint32 = 0xE389
2222 op_SLBGR uint32 = 0xB989
2223 op_SLBR uint32 = 0xB999
2224 op_SLDA uint32 = 0x8F00
2225 op_SLDL uint32 = 0x8D00
2226 op_SLDT uint32 = 0xED40
2227 op_SLFI uint32 = 0xC205
2228 op_SLG uint32 = 0xE30B
2229 op_SLGF uint32 = 0xE31B
2230 op_SLGFI uint32 = 0xC204
2231 op_SLGFR uint32 = 0xB91B
2232 op_SLGR uint32 = 0xB90B
2233 op_SLGRK uint32 = 0xB9EB
2234 op_SLHHHR uint32 = 0xB9CB
2235 op_SLHHLR uint32 = 0xB9DB
2236 op_SLL uint32 = 0x8900
2237 op_SLLG uint32 = 0xEB0D
2238 op_SLLK uint32 = 0xEBDF
2239 op_SLR uint32 = 0x1F00
2240 op_SLRK uint32 = 0xB9FB
2241 op_SLXT uint32 = 0xED48
2242 op_SLY uint32 = 0xE35F
2243 op_SP uint32 = 0xFB00
2244 op_SPKA uint32 = 0xB20A
2245 op_SPM uint32 = 0x0400
2246 op_SPT uint32 = 0xB208
2247 op_SPX uint32 = 0xB210
2248 op_SQD uint32 = 0xED35
2249 op_SQDB uint32 = 0xED15
2250 op_SQDBR uint32 = 0xB315
2251 op_SQDR uint32 = 0xB244
2252 op_SQE uint32 = 0xED34
2253 op_SQEB uint32 = 0xED14
2254 op_SQEBR uint32 = 0xB314
2255 op_SQER uint32 = 0xB245
2256 op_SQXBR uint32 = 0xB316
2257 op_SQXR uint32 = 0xB336
2258 op_SR uint32 = 0x1B00
2259 op_SRA uint32 = 0x8A00
2260 op_SRAG uint32 = 0xEB0A
2261 op_SRAK uint32 = 0xEBDC
2262 op_SRDA uint32 = 0x8E00
2263 op_SRDL uint32 = 0x8C00
2264 op_SRDT uint32 = 0xED41
2265 op_SRK uint32 = 0xB9F9
2266 op_SRL uint32 = 0x8800
2267 op_SRLG uint32 = 0xEB0C
2268 op_SRLK uint32 = 0xEBDE
2269 op_SRNM uint32 = 0xB299
2270 op_SRNMB uint32 = 0xB2B8
2271 op_SRNMT uint32 = 0xB2B9
2272 op_SRP uint32 = 0xF000
2273 op_SRST uint32 = 0xB25E
2274 op_SRSTU uint32 = 0xB9BE
2275 op_SRXT uint32 = 0xED49
2276 op_SSAIR uint32 = 0xB99F
2277 op_SSAR uint32 = 0xB225
2278 op_SSCH uint32 = 0xB233
2279 op_SSKE uint32 = 0xB22B
2280 op_SSM uint32 = 0x8000
2281 op_ST uint32 = 0x5000
2282 op_STAM uint32 = 0x9B00
2283 op_STAMY uint32 = 0xEB9B
2284 op_STAP uint32 = 0xB212
2285 op_STC uint32 = 0x4200
2286 op_STCH uint32 = 0xE3C3
2287 op_STCK uint32 = 0xB205
2288 op_STCKC uint32 = 0xB207
2289 op_STCKE uint32 = 0xB278
2290 op_STCKF uint32 = 0xB27C
2291 op_STCM uint32 = 0xBE00
2292 op_STCMH uint32 = 0xEB2C
2293 op_STCMY uint32 = 0xEB2D
2294 op_STCPS uint32 = 0xB23A
2295 op_STCRW uint32 = 0xB239
2296 op_STCTG uint32 = 0xEB25
2297 op_STCTL uint32 = 0xB600
2298 op_STCY uint32 = 0xE372
2299 op_STD uint32 = 0x6000
2300 op_STDY uint32 = 0xED67
2301 op_STE uint32 = 0x7000
2302 op_STEY uint32 = 0xED66
2303 op_STFH uint32 = 0xE3CB
2304 op_STFL uint32 = 0xB2B1
2305 op_STFLE uint32 = 0xB2B0
2306 op_STFPC uint32 = 0xB29C
2307 op_STG uint32 = 0xE324
2308 op_STGRL uint32 = 0xC40B
2309 op_STH uint32 = 0x4000
2310 op_STHH uint32 = 0xE3C7
2311 op_STHRL uint32 = 0xC407
2312 op_STHY uint32 = 0xE370
2313 op_STIDP uint32 = 0xB202
2314 op_STM uint32 = 0x9000
2315 op_STMG uint32 = 0xEB24
2316 op_STMH uint32 = 0xEB26
2317 op_STMY uint32 = 0xEB90
2318 op_STNSM uint32 = 0xAC00
2319 op_STOC uint32 = 0xEBF3
2320 op_STOCG uint32 = 0xEBE3
2321 op_STOSM uint32 = 0xAD00
2322 op_STPQ uint32 = 0xE38E
2323 op_STPT uint32 = 0xB209
2324 op_STPX uint32 = 0xB211
2325 op_STRAG uint32 = 0xE502
2326 op_STRL uint32 = 0xC40F
2327 op_STRV uint32 = 0xE33E
2328 op_STRVG uint32 = 0xE32F
2329 op_STRVH uint32 = 0xE33F
2330 op_STSCH uint32 = 0xB234
2331 op_STSI uint32 = 0xB27D
2332 op_STURA uint32 = 0xB246
2333 op_STURG uint32 = 0xB925
2334 op_STY uint32 = 0xE350
2335 op_SU uint32 = 0x7F00
2336 op_SUR uint32 = 0x3F00
2337 op_SVC uint32 = 0x0A00
2338 op_SW uint32 = 0x6F00
2339 op_SWR uint32 = 0x2F00
2340 op_SXBR uint32 = 0xB34B
2341 op_SXR uint32 = 0x3700
2342 op_SXTR uint32 = 0xB3DB
2343 op_SXTRA uint32 = 0xB3DB
2344 op_SY uint32 = 0xE35B
2345 op_TABORT uint32 = 0xB2FC
2346 op_TAM uint32 = 0x010B
2347 op_TAR uint32 = 0xB24C
2348 op_TB uint32 = 0xB22C
2349 op_TBDR uint32 = 0xB351
2350 op_TBEDR uint32 = 0xB350
2351 op_TBEGIN uint32 = 0xE560
2352 op_TBEGINC uint32 = 0xE561
2353 op_TCDB uint32 = 0xED11
2354 op_TCEB uint32 = 0xED10
2355 op_TCXB uint32 = 0xED12
2356 op_TDCDT uint32 = 0xED54
2357 op_TDCET uint32 = 0xED50
2358 op_TDCXT uint32 = 0xED58
2359 op_TDGDT uint32 = 0xED55
2360 op_TDGET uint32 = 0xED51
2361 op_TDGXT uint32 = 0xED59
2362 op_TEND uint32 = 0xB2F8
2363 op_THDER uint32 = 0xB358
2364 op_THDR uint32 = 0xB359
2365 op_TM uint32 = 0x9100
2366 op_TMH uint32 = 0xA700
2367 op_TMHH uint32 = 0xA702
2368 op_TMHL uint32 = 0xA703
2369 op_TML uint32 = 0xA701
2370 op_TMLH uint32 = 0xA700
2371 op_TMLL uint32 = 0xA701
2372 op_TMY uint32 = 0xEB51
2373 op_TP uint32 = 0xEBC0
2374 op_TPI uint32 = 0xB236
2375 op_TPROT uint32 = 0xE501
2376 op_TR uint32 = 0xDC00
2377 op_TRACE uint32 = 0x9900
2378 op_TRACG uint32 = 0xEB0F
2379 op_TRAP2 uint32 = 0x01FF
2380 op_TRAP4 uint32 = 0xB2FF
2381 op_TRE uint32 = 0xB2A5
2382 op_TROO uint32 = 0xB993
2383 op_TROT uint32 = 0xB992
2384 op_TRT uint32 = 0xDD00
2385 op_TRTE uint32 = 0xB9BF
2386 op_TRTO uint32 = 0xB991
2387 op_TRTR uint32 = 0xD000
2388 op_TRTRE uint32 = 0xB9BD
2389 op_TRTT uint32 = 0xB990
2390 op_TS uint32 = 0x9300
2391 op_TSCH uint32 = 0xB235
2392 op_UNPK uint32 = 0xF300
2393 op_UNPKA uint32 = 0xEA00
2394 op_UNPKU uint32 = 0xE200
2395 op_UPT uint32 = 0x0102
2396 op_X uint32 = 0x5700
2397 op_XC uint32 = 0xD700
2398 op_XG uint32 = 0xE382
2399 op_XGR uint32 = 0xB982
2400 op_XGRK uint32 = 0xB9E7
2401 op_XI uint32 = 0x9700
2402 op_XIHF uint32 = 0xC006
2403 op_XILF uint32 = 0xC007
2404 op_XIY uint32 = 0xEB57
2405 op_XR uint32 = 0x1700
2406 op_XRK uint32 = 0xB9F7
2407 op_XSCH uint32 = 0xB276
2408 op_XY uint32 = 0xE357
2409 op_ZAP uint32 = 0xF800
2410
2411
2412 op_CXPT uint32 = 0xEDAF
2413 op_CDPT uint32 = 0xEDAE
2414 op_CPXT uint32 = 0xEDAD
2415 op_CPDT uint32 = 0xEDAC
2416 op_LZRF uint32 = 0xE33B
2417 op_LZRG uint32 = 0xE32A
2418 op_LCCB uint32 = 0xE727
2419 op_LOCHHI uint32 = 0xEC4E
2420 op_LOCHI uint32 = 0xEC42
2421 op_LOCGHI uint32 = 0xEC46
2422 op_LOCFH uint32 = 0xEBE0
2423 op_LOCFHR uint32 = 0xB9E0
2424 op_LLZRGF uint32 = 0xE33A
2425 op_STOCFH uint32 = 0xEBE1
2426 op_VA uint32 = 0xE7F3
2427 op_VACC uint32 = 0xE7F1
2428 op_VAC uint32 = 0xE7BB
2429 op_VACCC uint32 = 0xE7B9
2430 op_VN uint32 = 0xE768
2431 op_VNC uint32 = 0xE769
2432 op_VAVG uint32 = 0xE7F2
2433 op_VAVGL uint32 = 0xE7F0
2434 op_VCKSM uint32 = 0xE766
2435 op_VCEQ uint32 = 0xE7F8
2436 op_VCH uint32 = 0xE7FB
2437 op_VCHL uint32 = 0xE7F9
2438 op_VCLZ uint32 = 0xE753
2439 op_VCTZ uint32 = 0xE752
2440 op_VEC uint32 = 0xE7DB
2441 op_VECL uint32 = 0xE7D9
2442 op_VERIM uint32 = 0xE772
2443 op_VERLL uint32 = 0xE733
2444 op_VERLLV uint32 = 0xE773
2445 op_VESLV uint32 = 0xE770
2446 op_VESL uint32 = 0xE730
2447 op_VESRA uint32 = 0xE73A
2448 op_VESRAV uint32 = 0xE77A
2449 op_VESRL uint32 = 0xE738
2450 op_VESRLV uint32 = 0xE778
2451 op_VX uint32 = 0xE76D
2452 op_VFAE uint32 = 0xE782
2453 op_VFEE uint32 = 0xE780
2454 op_VFENE uint32 = 0xE781
2455 op_VFA uint32 = 0xE7E3
2456 op_WFK uint32 = 0xE7CA
2457 op_VFCE uint32 = 0xE7E8
2458 op_VFCH uint32 = 0xE7EB
2459 op_VFCHE uint32 = 0xE7EA
2460 op_WFC uint32 = 0xE7CB
2461 op_VCDG uint32 = 0xE7C3
2462 op_VCDLG uint32 = 0xE7C1
2463 op_VCGD uint32 = 0xE7C2
2464 op_VCLGD uint32 = 0xE7C0
2465 op_VFD uint32 = 0xE7E5
2466 op_VLDE uint32 = 0xE7C4
2467 op_VLED uint32 = 0xE7C5
2468 op_VFM uint32 = 0xE7E7
2469 op_VFMA uint32 = 0xE78F
2470 op_VFMS uint32 = 0xE78E
2471 op_VFPSO uint32 = 0xE7CC
2472 op_VFSQ uint32 = 0xE7CE
2473 op_VFS uint32 = 0xE7E2
2474 op_VFTCI uint32 = 0xE74A
2475 op_VGFM uint32 = 0xE7B4
2476 op_VGFMA uint32 = 0xE7BC
2477 op_VGEF uint32 = 0xE713
2478 op_VGEG uint32 = 0xE712
2479 op_VGBM uint32 = 0xE744
2480 op_VGM uint32 = 0xE746
2481 op_VISTR uint32 = 0xE75C
2482 op_VL uint32 = 0xE706
2483 op_VLR uint32 = 0xE756
2484 op_VLREP uint32 = 0xE705
2485 op_VLC uint32 = 0xE7DE
2486 op_VLEH uint32 = 0xE701
2487 op_VLEF uint32 = 0xE703
2488 op_VLEG uint32 = 0xE702
2489 op_VLEB uint32 = 0xE700
2490 op_VLEIH uint32 = 0xE741
2491 op_VLEIF uint32 = 0xE743
2492 op_VLEIG uint32 = 0xE742
2493 op_VLEIB uint32 = 0xE740
2494 op_VFI uint32 = 0xE7C7
2495 op_VLGV uint32 = 0xE721
2496 op_VLLEZ uint32 = 0xE704
2497 op_VLM uint32 = 0xE736
2498 op_VLP uint32 = 0xE7DF
2499 op_VLBB uint32 = 0xE707
2500 op_VLVG uint32 = 0xE722
2501 op_VLVGP uint32 = 0xE762
2502 op_VLL uint32 = 0xE737
2503 op_VMX uint32 = 0xE7FF
2504 op_VMXL uint32 = 0xE7FD
2505 op_VMRH uint32 = 0xE761
2506 op_VMRL uint32 = 0xE760
2507 op_VMN uint32 = 0xE7FE
2508 op_VMNL uint32 = 0xE7FC
2509 op_VMAE uint32 = 0xE7AE
2510 op_VMAH uint32 = 0xE7AB
2511 op_VMALE uint32 = 0xE7AC
2512 op_VMALH uint32 = 0xE7A9
2513 op_VMALO uint32 = 0xE7AD
2514 op_VMAL uint32 = 0xE7AA
2515 op_VMAO uint32 = 0xE7AF
2516 op_VME uint32 = 0xE7A6
2517 op_VMH uint32 = 0xE7A3
2518 op_VMLE uint32 = 0xE7A4
2519 op_VMLH uint32 = 0xE7A1
2520 op_VMLO uint32 = 0xE7A5
2521 op_VML uint32 = 0xE7A2
2522 op_VMO uint32 = 0xE7A7
2523 op_VNO uint32 = 0xE76B
2524 op_VO uint32 = 0xE76A
2525 op_VPK uint32 = 0xE794
2526 op_VPKLS uint32 = 0xE795
2527 op_VPKS uint32 = 0xE797
2528 op_VPERM uint32 = 0xE78C
2529 op_VPDI uint32 = 0xE784
2530 op_VPOPCT uint32 = 0xE750
2531 op_VREP uint32 = 0xE74D
2532 op_VREPI uint32 = 0xE745
2533 op_VSCEF uint32 = 0xE71B
2534 op_VSCEG uint32 = 0xE71A
2535 op_VSEL uint32 = 0xE78D
2536 op_VSL uint32 = 0xE774
2537 op_VSLB uint32 = 0xE775
2538 op_VSLDB uint32 = 0xE777
2539 op_VSRA uint32 = 0xE77E
2540 op_VSRAB uint32 = 0xE77F
2541 op_VSRL uint32 = 0xE77C
2542 op_VSRLB uint32 = 0xE77D
2543 op_VSEG uint32 = 0xE75F
2544 op_VST uint32 = 0xE70E
2545 op_VSTEH uint32 = 0xE709
2546 op_VSTEF uint32 = 0xE70B
2547 op_VSTEG uint32 = 0xE70A
2548 op_VSTEB uint32 = 0xE708
2549 op_VSTM uint32 = 0xE73E
2550 op_VSTL uint32 = 0xE73F
2551 op_VSTRC uint32 = 0xE78A
2552 op_VS uint32 = 0xE7F7
2553 op_VSCBI uint32 = 0xE7F5
2554 op_VSBCBI uint32 = 0xE7BD
2555 op_VSBI uint32 = 0xE7BF
2556 op_VSUMG uint32 = 0xE765
2557 op_VSUMQ uint32 = 0xE767
2558 op_VSUM uint32 = 0xE764
2559 op_VTM uint32 = 0xE7D8
2560 op_VUPH uint32 = 0xE7D7
2561 op_VUPLH uint32 = 0xE7D5
2562 op_VUPLL uint32 = 0xE7D4
2563 op_VUPL uint32 = 0xE7D6
2564 op_VMSL uint32 = 0xE7B8
2565 )
2566
2567 func oclass(a *obj.Addr) int {
2568 return int(a.Class) - 1
2569 }
2570
2571
2572
2573 func (c *ctxtz) addrilreloc(sym *obj.LSym, add int64) *obj.Reloc {
2574 if sym == nil {
2575 c.ctxt.Diag("require symbol to apply relocation")
2576 }
2577 offset := int64(2)
2578 rel := obj.Addrel(c.cursym)
2579 rel.Off = int32(c.pc + offset)
2580 rel.Siz = 4
2581 rel.Sym = sym
2582 rel.Add = add + offset + int64(rel.Siz)
2583 rel.Type = objabi.R_PCRELDBL
2584 return rel
2585 }
2586
2587 func (c *ctxtz) addrilrelocoffset(sym *obj.LSym, add, offset int64) *obj.Reloc {
2588 if sym == nil {
2589 c.ctxt.Diag("require symbol to apply relocation")
2590 }
2591 offset += int64(2)
2592 rel := obj.Addrel(c.cursym)
2593 rel.Off = int32(c.pc + offset)
2594 rel.Siz = 4
2595 rel.Sym = sym
2596 rel.Add = add + offset + int64(rel.Siz)
2597 rel.Type = objabi.R_PCRELDBL
2598 return rel
2599 }
2600
2601
2602
2603 func (c *ctxtz) addcallreloc(sym *obj.LSym, add int64) *obj.Reloc {
2604 if sym == nil {
2605 c.ctxt.Diag("require symbol to apply relocation")
2606 }
2607 offset := int64(2)
2608 rel := obj.Addrel(c.cursym)
2609 rel.Off = int32(c.pc + offset)
2610 rel.Siz = 4
2611 rel.Sym = sym
2612 rel.Add = add + offset + int64(rel.Siz)
2613 rel.Type = objabi.R_CALL
2614 return rel
2615 }
2616
2617 func (c *ctxtz) branchMask(p *obj.Prog) uint32 {
2618 switch p.As {
2619 case ABEQ, ACMPBEQ, ACMPUBEQ, AMOVDEQ:
2620 return 0x8
2621 case ABGE, ACMPBGE, ACMPUBGE, AMOVDGE:
2622 return 0xA
2623 case ABGT, ACMPBGT, ACMPUBGT, AMOVDGT:
2624 return 0x2
2625 case ABLE, ACMPBLE, ACMPUBLE, AMOVDLE:
2626 return 0xC
2627 case ABLT, ACMPBLT, ACMPUBLT, AMOVDLT:
2628 return 0x4
2629 case ABNE, ACMPBNE, ACMPUBNE, AMOVDNE:
2630 return 0x7
2631 case ABLEU:
2632 return 0xD
2633 case ABLTU:
2634 return 0x5
2635 case ABVC:
2636 return 0x0
2637 case ABVS:
2638 return 0x1
2639 }
2640 c.ctxt.Diag("unknown conditional branch %v", p.As)
2641 return 0xF
2642 }
2643
2644 func (c *ctxtz) asmout(p *obj.Prog, asm *[]byte) {
2645 o := c.oplook(p)
2646
2647 if o == nil {
2648 return
2649 }
2650
2651 switch o.i {
2652 default:
2653 c.ctxt.Diag("unknown index %d", o.i)
2654
2655 case 0:
2656 break
2657
2658 case 1:
2659 switch p.As {
2660 default:
2661 c.ctxt.Diag("unhandled operation: %v", p.As)
2662 case AMOVD:
2663 zRRE(op_LGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2664
2665 case AMOVW:
2666 zRRE(op_LGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2667 case AMOVH:
2668 zRRE(op_LGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2669 case AMOVB:
2670 zRRE(op_LGBR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2671
2672 case AMOVWZ:
2673 zRRE(op_LLGFR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2674 case AMOVHZ:
2675 zRRE(op_LLGHR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2676 case AMOVBZ:
2677 zRRE(op_LLGCR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2678
2679 case AMOVDBR:
2680 zRRE(op_LRVGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2681 case AMOVWBR:
2682 zRRE(op_LRVR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2683
2684 case AFMOVD, AFMOVS:
2685 zRR(op_LDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2686 }
2687
2688 case 2:
2689 r := p.Reg
2690 if r == 0 {
2691 r = p.To.Reg
2692 }
2693
2694 var opcode uint32
2695
2696 switch p.As {
2697 default:
2698 c.ctxt.Diag("invalid opcode")
2699 case AADD:
2700 opcode = op_AGRK
2701 case AADDC:
2702 opcode = op_ALGRK
2703 case AADDE:
2704 opcode = op_ALCGR
2705 case AADDW:
2706 opcode = op_ARK
2707 case AMULLW:
2708 opcode = op_MSGFR
2709 case AMULLD:
2710 opcode = op_MSGR
2711 case ADIVW, AMODW:
2712 opcode = op_DSGFR
2713 case ADIVWU, AMODWU:
2714 opcode = op_DLR
2715 case ADIVD, AMODD:
2716 opcode = op_DSGR
2717 case ADIVDU, AMODDU:
2718 opcode = op_DLGR
2719 }
2720
2721 switch p.As {
2722 default:
2723
2724 case AADD, AADDC, AADDW:
2725 if p.As == AADDW && r == p.To.Reg {
2726 zRR(op_AR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2727 } else {
2728 zRRF(opcode, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2729 }
2730
2731 case AADDE, AMULLW, AMULLD:
2732 if r == p.To.Reg {
2733 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2734 } else if p.From.Reg == p.To.Reg {
2735 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
2736 } else {
2737 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2738 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2739 }
2740
2741 case ADIVW, ADIVWU, ADIVD, ADIVDU:
2742 if p.As == ADIVWU || p.As == ADIVDU {
2743 zRI(op_LGHI, REGTMP, 0, asm)
2744 }
2745 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2746 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm)
2747 zRRE(op_LGR, uint32(p.To.Reg), REGTMP2, asm)
2748
2749 case AMODW, AMODWU, AMODD, AMODDU:
2750 if p.As == AMODWU || p.As == AMODDU {
2751 zRI(op_LGHI, REGTMP, 0, asm)
2752 }
2753 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2754 zRRE(opcode, REGTMP, uint32(p.From.Reg), asm)
2755 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm)
2756
2757 }
2758
2759 case 3:
2760 v := c.vregoff(&p.From)
2761 switch p.As {
2762 case AMOVBZ:
2763 v = int64(uint8(v))
2764 case AMOVHZ:
2765 v = int64(uint16(v))
2766 case AMOVWZ:
2767 v = int64(uint32(v))
2768 case AMOVB:
2769 v = int64(int8(v))
2770 case AMOVH:
2771 v = int64(int16(v))
2772 case AMOVW:
2773 v = int64(int32(v))
2774 }
2775 if int64(int16(v)) == v {
2776 zRI(op_LGHI, uint32(p.To.Reg), uint32(v), asm)
2777 } else if v&0xffff0000 == v {
2778 zRI(op_LLILH, uint32(p.To.Reg), uint32(v>>16), asm)
2779 } else if v&0xffff00000000 == v {
2780 zRI(op_LLIHL, uint32(p.To.Reg), uint32(v>>32), asm)
2781 } else if uint64(v)&0xffff000000000000 == uint64(v) {
2782 zRI(op_LLIHH, uint32(p.To.Reg), uint32(v>>48), asm)
2783 } else if int64(int32(v)) == v {
2784 zRIL(_a, op_LGFI, uint32(p.To.Reg), uint32(v), asm)
2785 } else if int64(uint32(v)) == v {
2786 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2787 } else if uint64(v)&0xffffffff00000000 == uint64(v) {
2788 zRIL(_a, op_LLIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2789 } else {
2790 zRIL(_a, op_LLILF, uint32(p.To.Reg), uint32(v), asm)
2791 zRIL(_a, op_IIHF, uint32(p.To.Reg), uint32(v>>32), asm)
2792 }
2793
2794 case 4:
2795 r := p.Reg
2796 if r == 0 {
2797 r = p.To.Reg
2798 }
2799 zRRE(op_LGR, REGTMP2, uint32(r), asm)
2800 zRRE(op_MLGR, REGTMP, uint32(p.From.Reg), asm)
2801 switch p.As {
2802 case AMULHDU:
2803
2804 zRRE(op_LGR, uint32(p.To.Reg), REGTMP, asm)
2805 case AMULHD:
2806
2807
2808 zRSY(op_SRAG, REGTMP2, uint32(p.From.Reg), 0, 63, asm)
2809 zRRE(op_NGR, REGTMP2, uint32(r), asm)
2810 zRRE(op_SGR, REGTMP, REGTMP2, asm)
2811 zRSY(op_SRAG, REGTMP2, uint32(r), 0, 63, asm)
2812 zRRE(op_NGR, REGTMP2, uint32(p.From.Reg), asm)
2813 zRRF(op_SGRK, REGTMP2, 0, uint32(p.To.Reg), REGTMP, asm)
2814 }
2815
2816 case 5:
2817 zI(op_SVC, 0, asm)
2818
2819 case 6:
2820 var oprr, oprre, oprrf uint32
2821 switch p.As {
2822 case AAND:
2823 oprre = op_NGR
2824 oprrf = op_NGRK
2825 case AANDW:
2826 oprr = op_NR
2827 oprrf = op_NRK
2828 case AOR:
2829 oprre = op_OGR
2830 oprrf = op_OGRK
2831 case AORW:
2832 oprr = op_OR
2833 oprrf = op_ORK
2834 case AXOR:
2835 oprre = op_XGR
2836 oprrf = op_XGRK
2837 case AXORW:
2838 oprr = op_XR
2839 oprrf = op_XRK
2840 }
2841 if p.Reg == 0 {
2842 if oprr != 0 {
2843 zRR(oprr, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2844 } else {
2845 zRRE(oprre, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2846 }
2847 } else {
2848 zRRF(oprrf, uint32(p.Reg), 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2849 }
2850
2851 case 7:
2852 d2 := c.vregoff(&p.From)
2853 b2 := p.From.Reg
2854 r3 := p.Reg
2855 if r3 == 0 {
2856 r3 = p.To.Reg
2857 }
2858 r1 := p.To.Reg
2859 var opcode uint32
2860 switch p.As {
2861 default:
2862 case ASLD:
2863 opcode = op_SLLG
2864 case ASRD:
2865 opcode = op_SRLG
2866 case ASLW:
2867 opcode = op_SLLK
2868 case ASRW:
2869 opcode = op_SRLK
2870 case ARLL:
2871 opcode = op_RLL
2872 case ARLLG:
2873 opcode = op_RLLG
2874 case ASRAW:
2875 opcode = op_SRAK
2876 case ASRAD:
2877 opcode = op_SRAG
2878 }
2879 zRSY(opcode, uint32(r1), uint32(r3), uint32(b2), uint32(d2), asm)
2880
2881 case 8:
2882 if p.To.Reg&1 != 0 {
2883 c.ctxt.Diag("target must be an even-numbered register")
2884 }
2885
2886 zRRE(op_FLOGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2887
2888 case 9:
2889 zRRE(op_POPCNT, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2890
2891 case 10:
2892 r := int(p.Reg)
2893
2894 switch p.As {
2895 default:
2896 case ASUB:
2897 if r == 0 {
2898 zRRE(op_SGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2899 } else {
2900 zRRF(op_SGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2901 }
2902 case ASUBC:
2903 if r == 0 {
2904 zRRE(op_SLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2905 } else {
2906 zRRF(op_SLGRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2907 }
2908 case ASUBE:
2909 if r == 0 {
2910 r = int(p.To.Reg)
2911 }
2912 if r == int(p.To.Reg) {
2913 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2914 } else if p.From.Reg == p.To.Reg {
2915 zRRE(op_LGR, REGTMP, uint32(p.From.Reg), asm)
2916 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2917 zRRE(op_SLBGR, uint32(p.To.Reg), REGTMP, asm)
2918 } else {
2919 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
2920 zRRE(op_SLBGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2921 }
2922 case ASUBW:
2923 if r == 0 {
2924 zRR(op_SR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
2925 } else {
2926 zRRF(op_SRK, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(r), asm)
2927 }
2928 }
2929
2930 case 11:
2931 v := int32(0)
2932
2933 if p.Pcond != nil {
2934 v = int32((p.Pcond.Pc - p.Pc) >> 1)
2935 }
2936
2937 if p.As == ABR && p.To.Sym == nil && int32(int16(v)) == v {
2938 zRI(op_BRC, 0xF, uint32(v), asm)
2939 } else {
2940 if p.As == ABL {
2941 zRIL(_b, op_BRASL, uint32(REG_LR), uint32(v), asm)
2942 } else {
2943 zRIL(_c, op_BRCL, 0xF, uint32(v), asm)
2944 }
2945 if p.To.Sym != nil {
2946 c.addcallreloc(p.To.Sym, p.To.Offset)
2947 }
2948 }
2949
2950 case 12:
2951 r1 := p.To.Reg
2952 d2 := c.vregoff(&p.From)
2953 b2 := p.From.Reg
2954 if b2 == 0 {
2955 b2 = REGSP
2956 }
2957 x2 := p.From.Index
2958 if -DISP20/2 > d2 || d2 >= DISP20/2 {
2959 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm)
2960 if x2 != 0 {
2961 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm)
2962 }
2963 x2 = REGTMP
2964 d2 = 0
2965 }
2966 var opx, opxy uint32
2967 switch p.As {
2968 case AADD:
2969 opxy = op_AG
2970 case AADDC:
2971 opxy = op_ALG
2972 case AADDW:
2973 opx = op_A
2974 opxy = op_AY
2975 case AMULLW:
2976 opx = op_MS
2977 opxy = op_MSY
2978 case AMULLD:
2979 opxy = op_MSG
2980 case ASUB:
2981 opxy = op_SG
2982 case ASUBC:
2983 opxy = op_SLG
2984 case ASUBE:
2985 opxy = op_SLBG
2986 case ASUBW:
2987 opx = op_S
2988 opxy = op_SY
2989 case AAND:
2990 opxy = op_NG
2991 case AANDW:
2992 opx = op_N
2993 opxy = op_NY
2994 case AOR:
2995 opxy = op_OG
2996 case AORW:
2997 opx = op_O
2998 opxy = op_OY
2999 case AXOR:
3000 opxy = op_XG
3001 case AXORW:
3002 opx = op_X
3003 opxy = op_XY
3004 }
3005 if opx != 0 && 0 <= d2 && d2 < DISP12 {
3006 zRX(opx, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3007 } else {
3008 zRXY(opxy, uint32(r1), uint32(x2), uint32(b2), uint32(d2), asm)
3009 }
3010
3011 case 13:
3012 r1 := p.To.Reg
3013 r2 := p.RestArgs[2].Reg
3014 i3 := uint8(p.From.Offset)
3015 i4 := uint8(p.RestArgs[0].Offset)
3016 i5 := uint8(p.RestArgs[1].Offset)
3017 switch p.As {
3018 case ARNSBGT, ARXSBGT, AROSBGT:
3019 i3 |= 0x80
3020 case ARISBGZ, ARISBGNZ, ARISBHGZ, ARISBLGZ:
3021 i4 |= 0x80
3022 }
3023 var opcode uint32
3024 switch p.As {
3025 case ARNSBG, ARNSBGT:
3026 opcode = op_RNSBG
3027 case ARXSBG, ARXSBGT:
3028 opcode = op_RXSBG
3029 case AROSBG, AROSBGT:
3030 opcode = op_ROSBG
3031 case ARISBG, ARISBGZ:
3032 opcode = op_RISBG
3033 case ARISBGN, ARISBGNZ:
3034 opcode = op_RISBGN
3035 case ARISBHG, ARISBHGZ:
3036 opcode = op_RISBHG
3037 case ARISBLG, ARISBLGZ:
3038 opcode = op_RISBLG
3039 }
3040 zRIE(_f, uint32(opcode), uint32(r1), uint32(r2), 0, uint32(i3), uint32(i4), 0, uint32(i5), asm)
3041
3042 case 15:
3043 r := p.To.Reg
3044 if p.As == ABCL || p.As == ABL {
3045 zRR(op_BASR, uint32(REG_LR), uint32(r), asm)
3046 } else {
3047 zRR(op_BCR, 0xF, uint32(r), asm)
3048 }
3049
3050 case 16:
3051 v := int32(0)
3052 if p.Pcond != nil {
3053 v = int32((p.Pcond.Pc - p.Pc) >> 1)
3054 }
3055 mask := c.branchMask(p)
3056 if p.To.Sym == nil && int32(int16(v)) == v {
3057 zRI(op_BRC, mask, uint32(v), asm)
3058 } else {
3059 zRIL(_c, op_BRCL, mask, uint32(v), asm)
3060 }
3061 if p.To.Sym != nil {
3062 c.addrilreloc(p.To.Sym, p.To.Offset)
3063 }
3064
3065 case 17:
3066 m3 := c.branchMask(p)
3067 zRRF(op_LOCGR, m3, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3068
3069 case 18:
3070 if p.As == ABL {
3071 zRR(op_BASR, uint32(REG_LR), uint32(p.To.Reg), asm)
3072 } else {
3073 zRR(op_BCR, 0xF, uint32(p.To.Reg), asm)
3074 }
3075
3076 case 19:
3077 d := c.vregoff(&p.From)
3078 zRIL(_b, op_LARL, uint32(p.To.Reg), 0, asm)
3079 if d&1 != 0 {
3080 zRX(op_LA, uint32(p.To.Reg), uint32(p.To.Reg), 0, 1, asm)
3081 d -= 1
3082 }
3083 c.addrilreloc(p.From.Sym, d)
3084
3085 case 21:
3086 v := c.vregoff(&p.From)
3087 r := p.Reg
3088 if r == 0 {
3089 r = p.To.Reg
3090 }
3091 switch p.As {
3092 case ASUB:
3093 zRIL(_a, op_LGFI, uint32(REGTMP), uint32(v), asm)
3094 zRRF(op_SLGRK, uint32(REGTMP), 0, uint32(p.To.Reg), uint32(r), asm)
3095 case ASUBC:
3096 if r != p.To.Reg {
3097 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3098 }
3099 zRIL(_a, op_SLGFI, uint32(p.To.Reg), uint32(v), asm)
3100 case ASUBW:
3101 if r != p.To.Reg {
3102 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3103 }
3104 zRIL(_a, op_SLFI, uint32(p.To.Reg), uint32(v), asm)
3105 }
3106
3107 case 22:
3108 v := c.vregoff(&p.From)
3109 r := p.Reg
3110 if r == 0 {
3111 r = p.To.Reg
3112 }
3113 var opri, opril, oprie uint32
3114 switch p.As {
3115 case AADD:
3116 opri = op_AGHI
3117 opril = op_AGFI
3118 oprie = op_AGHIK
3119 case AADDC:
3120 opril = op_ALGFI
3121 oprie = op_ALGHSIK
3122 case AADDW:
3123 opri = op_AHI
3124 opril = op_AFI
3125 oprie = op_AHIK
3126 case AMULLW:
3127 opri = op_MHI
3128 opril = op_MSFI
3129 case AMULLD:
3130 opri = op_MGHI
3131 opril = op_MSGFI
3132 }
3133 if r != p.To.Reg && (oprie == 0 || int64(int16(v)) != v) {
3134 switch p.As {
3135 case AADD, AADDC, AMULLD:
3136 zRRE(op_LGR, uint32(p.To.Reg), uint32(r), asm)
3137 case AADDW, AMULLW:
3138 zRR(op_LR, uint32(p.To.Reg), uint32(r), asm)
3139 }
3140 r = p.To.Reg
3141 }
3142 if opri != 0 && r == p.To.Reg && int64(int16(v)) == v {
3143 zRI(opri, uint32(p.To.Reg), uint32(v), asm)
3144 } else if oprie != 0 && int64(int16(v)) == v {
3145 zRIE(_d, oprie, uint32(p.To.Reg), uint32(r), uint32(v), 0, 0, 0, 0, asm)
3146 } else {
3147 zRIL(_a, opril, uint32(p.To.Reg), uint32(v), asm)
3148 }
3149
3150 case 23:
3151
3152 v := c.vregoff(&p.From)
3153 switch p.As {
3154 default:
3155 c.ctxt.Diag("%v is not supported", p)
3156 case AAND:
3157 if v >= 0 {
3158 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3159 zRRE(op_NGR, uint32(p.To.Reg), REGTMP, asm)
3160 } else if int64(int16(v)) == v {
3161 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3162 } else {
3163 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3164 }
3165 case AOR:
3166 if int64(uint32(v)) != v {
3167 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3168 zRRE(op_OGR, uint32(p.To.Reg), REGTMP, asm)
3169 } else if int64(uint16(v)) == v {
3170 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3171 } else {
3172 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3173 }
3174 case AXOR:
3175 if int64(uint32(v)) != v {
3176 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3177 zRRE(op_XGR, uint32(p.To.Reg), REGTMP, asm)
3178 } else {
3179 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3180 }
3181 }
3182
3183 case 24:
3184 v := c.vregoff(&p.From)
3185 switch p.As {
3186 case AANDW:
3187 if uint32(v&0xffff0000) == 0xffff0000 {
3188 zRI(op_NILL, uint32(p.To.Reg), uint32(v), asm)
3189 } else if uint32(v&0x0000ffff) == 0x0000ffff {
3190 zRI(op_NILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3191 } else {
3192 zRIL(_a, op_NILF, uint32(p.To.Reg), uint32(v), asm)
3193 }
3194 case AORW:
3195 if uint32(v&0xffff0000) == 0 {
3196 zRI(op_OILL, uint32(p.To.Reg), uint32(v), asm)
3197 } else if uint32(v&0x0000ffff) == 0 {
3198 zRI(op_OILH, uint32(p.To.Reg), uint32(v)>>16, asm)
3199 } else {
3200 zRIL(_a, op_OILF, uint32(p.To.Reg), uint32(v), asm)
3201 }
3202 case AXORW:
3203 zRIL(_a, op_XILF, uint32(p.To.Reg), uint32(v), asm)
3204 }
3205
3206 case 26:
3207 v := c.regoff(&p.From)
3208 r := p.From.Reg
3209 if r == 0 {
3210 r = REGSP
3211 }
3212 i := p.From.Index
3213 if v >= 0 && v < DISP12 {
3214 zRX(op_LA, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3215 } else if v >= -DISP20/2 && v < DISP20/2 {
3216 zRXY(op_LAY, uint32(p.To.Reg), uint32(r), uint32(i), uint32(v), asm)
3217 } else {
3218 zRIL(_a, op_LGFI, REGTMP, uint32(v), asm)
3219 zRX(op_LA, uint32(p.To.Reg), uint32(r), REGTMP, uint32(i), asm)
3220 }
3221
3222 case 31:
3223 wd := uint64(c.vregoff(&p.From))
3224 *asm = append(*asm,
3225 uint8(wd>>56),
3226 uint8(wd>>48),
3227 uint8(wd>>40),
3228 uint8(wd>>32),
3229 uint8(wd>>24),
3230 uint8(wd>>16),
3231 uint8(wd>>8),
3232 uint8(wd))
3233
3234 case 32:
3235 var opcode uint32
3236 switch p.As {
3237 default:
3238 c.ctxt.Diag("invalid opcode")
3239 case AFADD:
3240 opcode = op_ADBR
3241 case AFADDS:
3242 opcode = op_AEBR
3243 case AFDIV:
3244 opcode = op_DDBR
3245 case AFDIVS:
3246 opcode = op_DEBR
3247 case AFMUL:
3248 opcode = op_MDBR
3249 case AFMULS:
3250 opcode = op_MEEBR
3251 case AFSUB:
3252 opcode = op_SDBR
3253 case AFSUBS:
3254 opcode = op_SEBR
3255 }
3256 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3257
3258 case 33:
3259 r := p.From.Reg
3260 if oclass(&p.From) == C_NONE {
3261 r = p.To.Reg
3262 }
3263 var opcode uint32
3264 switch p.As {
3265 default:
3266 case AFABS:
3267 opcode = op_LPDBR
3268 case AFNABS:
3269 opcode = op_LNDBR
3270 case ALPDFR:
3271 opcode = op_LPDFR
3272 case ALNDFR:
3273 opcode = op_LNDFR
3274 case AFNEG:
3275 opcode = op_LCDFR
3276 case AFNEGS:
3277 opcode = op_LCEBR
3278 case ALEDBR:
3279 opcode = op_LEDBR
3280 case ALDEBR:
3281 opcode = op_LDEBR
3282 case AFSQRT:
3283 opcode = op_SQDBR
3284 case AFSQRTS:
3285 opcode = op_SQEBR
3286 }
3287 zRRE(opcode, uint32(p.To.Reg), uint32(r), asm)
3288
3289 case 34:
3290 var opcode uint32
3291 switch p.As {
3292 default:
3293 c.ctxt.Diag("invalid opcode")
3294 case AFMADD:
3295 opcode = op_MADBR
3296 case AFMADDS:
3297 opcode = op_MAEBR
3298 case AFMSUB:
3299 opcode = op_MSDBR
3300 case AFMSUBS:
3301 opcode = op_MSEBR
3302 }
3303 zRRD(opcode, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
3304
3305 case 35:
3306 d2 := c.regoff(&p.To)
3307 b2 := p.To.Reg
3308 if b2 == 0 {
3309 b2 = REGSP
3310 }
3311 x2 := p.To.Index
3312 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3313 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm)
3314 if x2 != 0 {
3315 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm)
3316 }
3317 x2 = REGTMP
3318 d2 = 0
3319 }
3320 zRXY(c.zopstore(p.As), uint32(p.From.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3321
3322 case 36:
3323 d2 := c.regoff(&p.From)
3324 b2 := p.From.Reg
3325 if b2 == 0 {
3326 b2 = REGSP
3327 }
3328 x2 := p.From.Index
3329 if d2 < -DISP20/2 || d2 >= DISP20/2 {
3330 zRIL(_a, op_LGFI, REGTMP, uint32(d2), asm)
3331 if x2 != 0 {
3332 zRX(op_LA, REGTMP, REGTMP, uint32(x2), 0, asm)
3333 }
3334 x2 = REGTMP
3335 d2 = 0
3336 }
3337 zRXY(c.zopload(p.As), uint32(p.To.Reg), uint32(x2), uint32(b2), uint32(d2), asm)
3338
3339 case 40:
3340 wd := uint32(c.regoff(&p.From))
3341 if p.As == AWORD {
3342 *asm = append(*asm, uint8(wd>>24), uint8(wd>>16), uint8(wd>>8), uint8(wd))
3343 } else {
3344 *asm = append(*asm, uint8(wd))
3345 }
3346
3347 case 47:
3348 r := p.From.Reg
3349 if r == 0 {
3350 r = p.To.Reg
3351 }
3352 switch p.As {
3353 case ANEG:
3354 zRRE(op_LCGR, uint32(p.To.Reg), uint32(r), asm)
3355 case ANEGW:
3356 zRRE(op_LCGFR, uint32(p.To.Reg), uint32(r), asm)
3357 }
3358
3359 case 48:
3360 m3 := c.vregoff(&p.From)
3361 if 0 > m3 || m3 > 7 {
3362 c.ctxt.Diag("mask (%v) must be in the range [0, 7]", m3)
3363 }
3364 var opcode uint32
3365 switch p.As {
3366 case AFIEBR:
3367 opcode = op_FIEBR
3368 case AFIDBR:
3369 opcode = op_FIDBR
3370 }
3371 zRRF(opcode, uint32(m3), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3372
3373 case 49:
3374 zRRF(op_CPSDR, uint32(p.From.Reg), 0, uint32(p.To.Reg), uint32(p.Reg), asm)
3375
3376 case 50:
3377 var opcode uint32
3378 switch p.As {
3379 case ALTEBR:
3380 opcode = op_LTEBR
3381 case ALTDBR:
3382 opcode = op_LTDBR
3383 }
3384 zRRE(opcode, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3385
3386 case 51:
3387 var opcode uint32
3388 switch p.As {
3389 case ATCEB:
3390 opcode = op_TCEB
3391 case ATCDB:
3392 opcode = op_TCDB
3393 }
3394 d2 := c.regoff(&p.To)
3395 zRXE(opcode, uint32(p.From.Reg), 0, 0, uint32(d2), 0, asm)
3396
3397 case 67:
3398 var opcode uint32
3399 switch p.As {
3400 case AFMOVS:
3401 opcode = op_LZER
3402 case AFMOVD:
3403 opcode = op_LZDR
3404 }
3405 zRRE(opcode, uint32(p.To.Reg), 0, asm)
3406
3407 case 68:
3408 zRRE(op_EAR, uint32(p.To.Reg), uint32(p.From.Reg-REG_AR0), asm)
3409
3410 case 69:
3411 zRRE(op_SAR, uint32(p.To.Reg-REG_AR0), uint32(p.From.Reg), asm)
3412
3413 case 70:
3414 if p.As == ACMPW || p.As == ACMPWU {
3415 zRR(c.zoprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3416 } else {
3417 zRRE(c.zoprre(p.As), uint32(p.From.Reg), uint32(p.To.Reg), asm)
3418 }
3419
3420 case 71:
3421 v := c.vregoff(&p.To)
3422 switch p.As {
3423 case ACMP, ACMPW:
3424 if int64(int32(v)) != v {
3425 c.ctxt.Diag("%v overflows an int32", v)
3426 }
3427 case ACMPU, ACMPWU:
3428 if int64(uint32(v)) != v {
3429 c.ctxt.Diag("%v overflows a uint32", v)
3430 }
3431 }
3432 if p.As == ACMP && int64(int16(v)) == v {
3433 zRI(op_CGHI, uint32(p.From.Reg), uint32(v), asm)
3434 } else if p.As == ACMPW && int64(int16(v)) == v {
3435 zRI(op_CHI, uint32(p.From.Reg), uint32(v), asm)
3436 } else {
3437 zRIL(_a, c.zopril(p.As), uint32(p.From.Reg), uint32(v), asm)
3438 }
3439
3440 case 72:
3441 v := c.regoff(&p.From)
3442 d := c.regoff(&p.To)
3443 r := p.To.Reg
3444 if p.To.Index != 0 {
3445 c.ctxt.Diag("cannot use index register")
3446 }
3447 if r == 0 {
3448 r = REGSP
3449 }
3450 var opcode uint32
3451 switch p.As {
3452 case AMOVD:
3453 opcode = op_MVGHI
3454 case AMOVW, AMOVWZ:
3455 opcode = op_MVHI
3456 case AMOVH, AMOVHZ:
3457 opcode = op_MVHHI
3458 case AMOVB, AMOVBZ:
3459 opcode = op_MVI
3460 }
3461 if d < 0 || d >= DISP12 {
3462 if r == REGTMP {
3463 c.ctxt.Diag("displacement must be in range [0, 4096) to use %v", r)
3464 }
3465 if d >= -DISP20/2 && d < DISP20/2 {
3466 if opcode == op_MVI {
3467 opcode = op_MVIY
3468 } else {
3469 zRXY(op_LAY, uint32(REGTMP), 0, uint32(r), uint32(d), asm)
3470 r = REGTMP
3471 d = 0
3472 }
3473 } else {
3474 zRIL(_a, op_LGFI, REGTMP, uint32(d), asm)
3475 zRX(op_LA, REGTMP, REGTMP, uint32(r), 0, asm)
3476 r = REGTMP
3477 d = 0
3478 }
3479 }
3480 switch opcode {
3481 case op_MVI:
3482 zSI(opcode, uint32(v), uint32(r), uint32(d), asm)
3483 case op_MVIY:
3484 zSIY(opcode, uint32(v), uint32(r), uint32(d), asm)
3485 default:
3486 zSIL(opcode, uint32(r), uint32(d), uint32(v), asm)
3487 }
3488
3489 case 74:
3490 i2 := c.regoff(&p.To)
3491 switch p.As {
3492 case AMOVD:
3493 zRIL(_b, op_STGRL, uint32(p.From.Reg), 0, asm)
3494 case AMOVW, AMOVWZ:
3495 zRIL(_b, op_STRL, uint32(p.From.Reg), 0, asm)
3496 case AMOVH, AMOVHZ:
3497 zRIL(_b, op_STHRL, uint32(p.From.Reg), 0, asm)
3498 case AMOVB, AMOVBZ:
3499 zRIL(_b, op_LARL, REGTMP, 0, asm)
3500 adj := uint32(0)
3501 if i2&1 != 0 {
3502 i2 -= 1
3503 adj = 1
3504 }
3505 zRX(op_STC, uint32(p.From.Reg), 0, REGTMP, adj, asm)
3506 case AFMOVD:
3507 zRIL(_b, op_LARL, REGTMP, 0, asm)
3508 zRX(op_STD, uint32(p.From.Reg), 0, REGTMP, 0, asm)
3509 case AFMOVS:
3510 zRIL(_b, op_LARL, REGTMP, 0, asm)
3511 zRX(op_STE, uint32(p.From.Reg), 0, REGTMP, 0, asm)
3512 }
3513 c.addrilreloc(p.To.Sym, int64(i2))
3514
3515 case 75:
3516 i2 := c.regoff(&p.From)
3517 switch p.As {
3518 case AMOVD:
3519 if i2&1 != 0 {
3520 zRIL(_b, op_LARL, REGTMP, 0, asm)
3521 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 1, asm)
3522 i2 -= 1
3523 } else {
3524 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3525 }
3526 case AMOVW:
3527 zRIL(_b, op_LGFRL, uint32(p.To.Reg), 0, asm)
3528 case AMOVWZ:
3529 zRIL(_b, op_LLGFRL, uint32(p.To.Reg), 0, asm)
3530 case AMOVH:
3531 zRIL(_b, op_LGHRL, uint32(p.To.Reg), 0, asm)
3532 case AMOVHZ:
3533 zRIL(_b, op_LLGHRL, uint32(p.To.Reg), 0, asm)
3534 case AMOVB, AMOVBZ:
3535 zRIL(_b, op_LARL, REGTMP, 0, asm)
3536 adj := uint32(0)
3537 if i2&1 != 0 {
3538 i2 -= 1
3539 adj = 1
3540 }
3541 switch p.As {
3542 case AMOVB:
3543 zRXY(op_LGB, uint32(p.To.Reg), 0, REGTMP, adj, asm)
3544 case AMOVBZ:
3545 zRXY(op_LLGC, uint32(p.To.Reg), 0, REGTMP, adj, asm)
3546 }
3547 case AFMOVD:
3548 zRIL(_a, op_LARL, REGTMP, 0, asm)
3549 zRX(op_LD, uint32(p.To.Reg), 0, REGTMP, 0, asm)
3550 case AFMOVS:
3551 zRIL(_a, op_LARL, REGTMP, 0, asm)
3552 zRX(op_LE, uint32(p.To.Reg), 0, REGTMP, 0, asm)
3553 }
3554 c.addrilreloc(p.From.Sym, int64(i2))
3555
3556 case 77:
3557 if p.From.Offset > 255 || p.From.Offset < 1 {
3558 c.ctxt.Diag("illegal system call; system call number out of range: %v", p)
3559 zE(op_TRAP2, asm)
3560 } else {
3561 zI(op_SVC, uint32(p.From.Offset), asm)
3562 }
3563
3564 case 78:
3565
3566
3567 *asm = append(*asm, 0, 0, 0, 0)
3568
3569 case 79:
3570 v := c.regoff(&p.To)
3571 if v < 0 {
3572 v = 0
3573 }
3574 if p.As == ACS {
3575 zRS(op_CS, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3576 } else if p.As == ACSG {
3577 zRSY(op_CSG, uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg), uint32(v), asm)
3578 }
3579
3580 case 80:
3581 zRR(op_BCR, 0xE, 0, asm)
3582
3583 case 81:
3584 switch p.As {
3585 case ALDGR:
3586 zRRE(op_LDGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3587 case ALGDR:
3588 zRRE(op_LGDR, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3589 }
3590
3591 case 82:
3592 var opcode uint32
3593 switch p.As {
3594 default:
3595 log.Fatalf("unexpected opcode %v", p.As)
3596 case ACEFBRA:
3597 opcode = op_CEFBRA
3598 case ACDFBRA:
3599 opcode = op_CDFBRA
3600 case ACEGBRA:
3601 opcode = op_CEGBRA
3602 case ACDGBRA:
3603 opcode = op_CDGBRA
3604 case ACELFBR:
3605 opcode = op_CELFBR
3606 case ACDLFBR:
3607 opcode = op_CDLFBR
3608 case ACELGBR:
3609 opcode = op_CELGBR
3610 case ACDLGBR:
3611 opcode = op_CDLGBR
3612 }
3613
3614
3615
3616
3617 zRRF(opcode, 0, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3618
3619 case 83:
3620 var opcode uint32
3621 switch p.As {
3622 default:
3623 log.Fatalf("unexpected opcode %v", p.As)
3624 case ACFEBRA:
3625 opcode = op_CFEBRA
3626 case ACFDBRA:
3627 opcode = op_CFDBRA
3628 case ACGEBRA:
3629 opcode = op_CGEBRA
3630 case ACGDBRA:
3631 opcode = op_CGDBRA
3632 case ACLFEBR:
3633 opcode = op_CLFEBR
3634 case ACLFDBR:
3635 opcode = op_CLFDBR
3636 case ACLGEBR:
3637 opcode = op_CLGEBR
3638 case ACLGDBR:
3639 opcode = op_CLGDBR
3640 }
3641
3642
3643 zRRF(opcode, 5, 0, uint32(p.To.Reg), uint32(p.From.Reg), asm)
3644
3645 case 84:
3646 l := c.regoff(&p.From)
3647 if l < 1 || l > 256 {
3648 c.ctxt.Diag("number of bytes (%v) not in range [1,256]", l)
3649 }
3650 if p.GetFrom3().Index != 0 || p.To.Index != 0 {
3651 c.ctxt.Diag("cannot use index reg")
3652 }
3653 b1 := p.To.Reg
3654 b2 := p.GetFrom3().Reg
3655 if b1 == 0 {
3656 b1 = REGSP
3657 }
3658 if b2 == 0 {
3659 b2 = REGSP
3660 }
3661 d1 := c.regoff(&p.To)
3662 d2 := c.regoff(p.GetFrom3())
3663 if d1 < 0 || d1 >= DISP12 {
3664 if b2 == REGTMP {
3665 c.ctxt.Diag("REGTMP conflict")
3666 }
3667 if b1 != REGTMP {
3668 zRRE(op_LGR, REGTMP, uint32(b1), asm)
3669 }
3670 zRIL(_a, op_AGFI, REGTMP, uint32(d1), asm)
3671 if d1 == d2 && b1 == b2 {
3672 d2 = 0
3673 b2 = REGTMP
3674 }
3675 d1 = 0
3676 b1 = REGTMP
3677 }
3678 if d2 < 0 || d2 >= DISP12 {
3679 if b1 == REGTMP2 {
3680 c.ctxt.Diag("REGTMP2 conflict")
3681 }
3682 if b2 != REGTMP2 {
3683 zRRE(op_LGR, REGTMP2, uint32(b2), asm)
3684 }
3685 zRIL(_a, op_AGFI, REGTMP2, uint32(d2), asm)
3686 d2 = 0
3687 b2 = REGTMP2
3688 }
3689 var opcode uint32
3690 switch p.As {
3691 default:
3692 c.ctxt.Diag("unexpected opcode %v", p.As)
3693 case AMVC:
3694 opcode = op_MVC
3695 case ACLC:
3696 opcode = op_CLC
3697
3698 b1, b2 = b2, b1
3699 d1, d2 = d2, d1
3700 case AXC:
3701 opcode = op_XC
3702 case AOC:
3703 opcode = op_OC
3704 case ANC:
3705 opcode = op_NC
3706 }
3707 zSS(_a, opcode, uint32(l-1), 0, uint32(b1), uint32(d1), uint32(b2), uint32(d2), asm)
3708
3709 case 85:
3710 v := c.regoff(&p.From)
3711 if p.From.Sym == nil {
3712 if (v & 1) != 0 {
3713 c.ctxt.Diag("cannot use LARL with odd offset: %v", v)
3714 }
3715 } else {
3716 c.addrilreloc(p.From.Sym, int64(v))
3717 v = 0
3718 }
3719 zRIL(_b, op_LARL, uint32(p.To.Reg), uint32(v>>1), asm)
3720
3721 case 86:
3722 d := c.vregoff(&p.From)
3723 x := p.From.Index
3724 b := p.From.Reg
3725 if b == 0 {
3726 b = REGSP
3727 }
3728 switch p.As {
3729 case ALA:
3730 zRX(op_LA, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3731 case ALAY:
3732 zRXY(op_LAY, uint32(p.To.Reg), uint32(x), uint32(b), uint32(d), asm)
3733 }
3734
3735 case 87:
3736 v := c.vregoff(&p.From)
3737 if p.From.Sym == nil {
3738 if v&1 != 0 {
3739 c.ctxt.Diag("cannot use EXRL with odd offset: %v", v)
3740 }
3741 } else {
3742 c.addrilreloc(p.From.Sym, v)
3743 v = 0
3744 }
3745 zRIL(_b, op_EXRL, uint32(p.To.Reg), uint32(v>>1), asm)
3746
3747 case 88:
3748 var opcode uint32
3749 switch p.As {
3750 case ASTCK:
3751 opcode = op_STCK
3752 case ASTCKC:
3753 opcode = op_STCKC
3754 case ASTCKE:
3755 opcode = op_STCKE
3756 case ASTCKF:
3757 opcode = op_STCKF
3758 }
3759 v := c.vregoff(&p.To)
3760 r := p.To.Reg
3761 if r == 0 {
3762 r = REGSP
3763 }
3764 zS(opcode, uint32(r), uint32(v), asm)
3765
3766 case 89:
3767 var v int32
3768 if p.Pcond != nil {
3769 v = int32((p.Pcond.Pc - p.Pc) >> 1)
3770 }
3771 var opcode, opcode2 uint32
3772 switch p.As {
3773 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3774 opcode = op_CGRJ
3775 opcode2 = op_CGR
3776 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3777 opcode = op_CLGRJ
3778 opcode2 = op_CLGR
3779 }
3780 mask := c.branchMask(p)
3781 if int32(int16(v)) != v {
3782 zRRE(opcode2, uint32(p.From.Reg), uint32(p.Reg), asm)
3783 zRIL(_c, op_BRCL, mask, uint32(v-sizeRRE/2), asm)
3784 } else {
3785 zRIE(_b, opcode, uint32(p.From.Reg), uint32(p.Reg), uint32(v), 0, 0, mask, 0, asm)
3786 }
3787
3788 case 90:
3789 var v int32
3790 if p.Pcond != nil {
3791 v = int32((p.Pcond.Pc - p.Pc) >> 1)
3792 }
3793 var opcode, opcode2 uint32
3794 switch p.As {
3795 case ACMPBEQ, ACMPBGE, ACMPBGT, ACMPBLE, ACMPBLT, ACMPBNE:
3796 opcode = op_CGIJ
3797 opcode2 = op_CGFI
3798 case ACMPUBEQ, ACMPUBGE, ACMPUBGT, ACMPUBLE, ACMPUBLT, ACMPUBNE:
3799 opcode = op_CLGIJ
3800 opcode2 = op_CLGFI
3801 }
3802 mask := c.branchMask(p)
3803 if int32(int16(v)) != v {
3804 zRIL(_a, opcode2, uint32(p.From.Reg), uint32(c.regoff(p.GetFrom3())), asm)
3805 zRIL(_c, op_BRCL, mask, uint32(v-sizeRIL/2), asm)
3806 } else {
3807 zRIE(_c, opcode, uint32(p.From.Reg), mask, uint32(v), 0, 0, 0, uint32(c.regoff(p.GetFrom3())), asm)
3808 }
3809
3810 case 91:
3811 var opcode uint32
3812 switch p.As {
3813 case ATMHH:
3814 opcode = op_TMHH
3815 case ATMHL:
3816 opcode = op_TMHL
3817 case ATMLH:
3818 opcode = op_TMLH
3819 case ATMLL:
3820 opcode = op_TMLL
3821 }
3822 zRI(opcode, uint32(p.From.Reg), uint32(c.vregoff(&p.To)), asm)
3823
3824 case 92:
3825 zRRE(op_IPM, uint32(p.From.Reg), 0, asm)
3826
3827 case 93:
3828 v := c.vregoff(&p.To)
3829 if v != 0 {
3830 c.ctxt.Diag("invalid offset against GOT slot %v", p)
3831 }
3832 zRIL(_b, op_LGRL, uint32(p.To.Reg), 0, asm)
3833 rel := obj.Addrel(c.cursym)
3834 rel.Off = int32(c.pc + 2)
3835 rel.Siz = 4
3836 rel.Sym = p.From.Sym
3837 rel.Type = objabi.R_GOTPCREL
3838 rel.Add = 2 + int64(rel.Siz)
3839
3840 case 94:
3841 zRIL(_b, op_LARL, REGTMP, (sizeRIL+sizeRXY+sizeRI)>>1, asm)
3842 zRXY(op_LG, uint32(p.To.Reg), REGTMP, 0, 0, asm)
3843 zRI(op_BRC, 0xF, (sizeRI+8)>>1, asm)
3844 *asm = append(*asm, 0, 0, 0, 0, 0, 0, 0, 0)
3845 rel := obj.Addrel(c.cursym)
3846 rel.Off = int32(c.pc + sizeRIL + sizeRXY + sizeRI)
3847 rel.Siz = 8
3848 rel.Sym = p.From.Sym
3849 rel.Type = objabi.R_TLS_LE
3850 rel.Add = 0
3851
3852 case 95:
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864 zRIL(_b, op_LARL, REGTMP, 0, asm)
3865 ieent := obj.Addrel(c.cursym)
3866 ieent.Off = int32(c.pc + 2)
3867 ieent.Siz = 4
3868 ieent.Sym = p.From.Sym
3869 ieent.Type = objabi.R_TLS_IE
3870 ieent.Add = 2 + int64(ieent.Siz)
3871
3872
3873 zRXY(op_LGF, uint32(p.To.Reg), REGTMP, 0, 0, asm)
3874
3875
3876
3877 case 96:
3878 length := c.vregoff(&p.From)
3879 offset := c.vregoff(&p.To)
3880 reg := p.To.Reg
3881 if reg == 0 {
3882 reg = REGSP
3883 }
3884 if length <= 0 {
3885 c.ctxt.Diag("cannot CLEAR %d bytes, must be greater than 0", length)
3886 }
3887 for length > 0 {
3888 if offset < 0 || offset >= DISP12 {
3889 if offset >= -DISP20/2 && offset < DISP20/2 {
3890 zRXY(op_LAY, REGTMP, uint32(reg), 0, uint32(offset), asm)
3891 } else {
3892 if reg != REGTMP {
3893 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3894 }
3895 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3896 }
3897 reg = REGTMP
3898 offset = 0
3899 }
3900 size := length
3901 if size > 256 {
3902 size = 256
3903 }
3904
3905 switch size {
3906 case 1:
3907 zSI(op_MVI, 0, uint32(reg), uint32(offset), asm)
3908 case 2:
3909 zSIL(op_MVHHI, uint32(reg), uint32(offset), 0, asm)
3910 case 4:
3911 zSIL(op_MVHI, uint32(reg), uint32(offset), 0, asm)
3912 case 8:
3913 zSIL(op_MVGHI, uint32(reg), uint32(offset), 0, asm)
3914 default:
3915 zSS(_a, op_XC, uint32(size-1), 0, uint32(reg), uint32(offset), uint32(reg), uint32(offset), asm)
3916 }
3917
3918 length -= size
3919 offset += size
3920 }
3921
3922 case 97:
3923 rstart := p.From.Reg
3924 rend := p.Reg
3925 offset := c.regoff(&p.To)
3926 reg := p.To.Reg
3927 if reg == 0 {
3928 reg = REGSP
3929 }
3930 if offset < -DISP20/2 || offset >= DISP20/2 {
3931 if reg != REGTMP {
3932 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3933 }
3934 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3935 reg = REGTMP
3936 offset = 0
3937 }
3938 switch p.As {
3939 case ASTMY:
3940 if offset >= 0 && offset < DISP12 {
3941 zRS(op_STM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3942 } else {
3943 zRSY(op_STMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3944 }
3945 case ASTMG:
3946 zRSY(op_STMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3947 }
3948
3949 case 98:
3950 rstart := p.Reg
3951 rend := p.To.Reg
3952 offset := c.regoff(&p.From)
3953 reg := p.From.Reg
3954 if reg == 0 {
3955 reg = REGSP
3956 }
3957 if offset < -DISP20/2 || offset >= DISP20/2 {
3958 if reg != REGTMP {
3959 zRRE(op_LGR, REGTMP, uint32(reg), asm)
3960 }
3961 zRIL(_a, op_AGFI, REGTMP, uint32(offset), asm)
3962 reg = REGTMP
3963 offset = 0
3964 }
3965 switch p.As {
3966 case ALMY:
3967 if offset >= 0 && offset < DISP12 {
3968 zRS(op_LM, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3969 } else {
3970 zRSY(op_LMY, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3971 }
3972 case ALMG:
3973 zRSY(op_LMG, uint32(rstart), uint32(rend), uint32(reg), uint32(offset), asm)
3974 }
3975
3976 case 99:
3977 if p.To.Index != 0 {
3978 c.ctxt.Diag("cannot use indexed address")
3979 }
3980 offset := c.regoff(&p.To)
3981 if offset < -DISP20/2 || offset >= DISP20/2 {
3982 c.ctxt.Diag("%v does not fit into 20-bit signed integer", offset)
3983 }
3984 var opcode uint32
3985 switch p.As {
3986 case ALAA:
3987 opcode = op_LAA
3988 case ALAAG:
3989 opcode = op_LAAG
3990 case ALAAL:
3991 opcode = op_LAAL
3992 case ALAALG:
3993 opcode = op_LAALG
3994 case ALAN:
3995 opcode = op_LAN
3996 case ALANG:
3997 opcode = op_LANG
3998 case ALAX:
3999 opcode = op_LAX
4000 case ALAXG:
4001 opcode = op_LAXG
4002 case ALAO:
4003 opcode = op_LAO
4004 case ALAOG:
4005 opcode = op_LAOG
4006 }
4007 zRSY(opcode, uint32(p.Reg), uint32(p.From.Reg), uint32(p.To.Reg), uint32(offset), asm)
4008
4009 case 100:
4010 op, m3, _ := vop(p.As)
4011 v1 := p.From.Reg
4012 if p.Reg != 0 {
4013 m3 = uint32(c.vregoff(&p.From))
4014 v1 = p.Reg
4015 }
4016 b2 := p.To.Reg
4017 if b2 == 0 {
4018 b2 = REGSP
4019 }
4020 d2 := uint32(c.vregoff(&p.To))
4021 zVRX(op, uint32(v1), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4022
4023 case 101:
4024 op, m3, _ := vop(p.As)
4025 src := &p.From
4026 if p.GetFrom3() != nil {
4027 m3 = uint32(c.vregoff(&p.From))
4028 src = p.GetFrom3()
4029 }
4030 b2 := src.Reg
4031 if b2 == 0 {
4032 b2 = REGSP
4033 }
4034 d2 := uint32(c.vregoff(src))
4035 zVRX(op, uint32(p.To.Reg), uint32(src.Index), uint32(b2), d2, m3, asm)
4036
4037 case 102:
4038 op, _, _ := vop(p.As)
4039 m3 := uint32(c.vregoff(&p.From))
4040 b2 := p.To.Reg
4041 if b2 == 0 {
4042 b2 = REGSP
4043 }
4044 d2 := uint32(c.vregoff(&p.To))
4045 zVRV(op, uint32(p.Reg), uint32(p.To.Index), uint32(b2), d2, m3, asm)
4046
4047 case 103:
4048 op, _, _ := vop(p.As)
4049 m3 := uint32(c.vregoff(&p.From))
4050 b2 := p.GetFrom3().Reg
4051 if b2 == 0 {
4052 b2 = REGSP
4053 }
4054 d2 := uint32(c.vregoff(p.GetFrom3()))
4055 zVRV(op, uint32(p.To.Reg), uint32(p.GetFrom3().Index), uint32(b2), d2, m3, asm)
4056
4057 case 104:
4058 op, m4, _ := vop(p.As)
4059 fr := p.Reg
4060 if fr == 0 {
4061 fr = p.To.Reg
4062 }
4063 bits := uint32(c.vregoff(&p.From))
4064 zVRS(op, uint32(p.To.Reg), uint32(fr), uint32(p.From.Reg), bits, m4, asm)
4065
4066 case 105:
4067 op, _, _ := vop(p.As)
4068 offset := uint32(c.vregoff(&p.To))
4069 reg := p.To.Reg
4070 if reg == 0 {
4071 reg = REGSP
4072 }
4073 zVRS(op, uint32(p.From.Reg), uint32(p.Reg), uint32(reg), offset, 0, asm)
4074
4075 case 106:
4076 op, _, _ := vop(p.As)
4077 offset := uint32(c.vregoff(&p.From))
4078 reg := p.From.Reg
4079 if reg == 0 {
4080 reg = REGSP
4081 }
4082 zVRS(op, uint32(p.Reg), uint32(p.To.Reg), uint32(reg), offset, 0, asm)
4083
4084 case 107:
4085 op, _, _ := vop(p.As)
4086 offset := uint32(c.vregoff(&p.To))
4087 reg := p.To.Reg
4088 if reg == 0 {
4089 reg = REGSP
4090 }
4091 zVRS(op, uint32(p.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4092
4093 case 108:
4094 op, _, _ := vop(p.As)
4095 offset := uint32(c.vregoff(p.GetFrom3()))
4096 reg := p.GetFrom3().Reg
4097 if reg == 0 {
4098 reg = REGSP
4099 }
4100 zVRS(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(reg), offset, 0, asm)
4101
4102 case 109:
4103 op, m3, _ := vop(p.As)
4104 i2 := uint32(c.vregoff(&p.From))
4105 if p.GetFrom3() != nil {
4106 m3 = uint32(c.vregoff(&p.From))
4107 i2 = uint32(c.vregoff(p.GetFrom3()))
4108 }
4109 switch p.As {
4110 case AVZERO:
4111 i2 = 0
4112 case AVONE:
4113 i2 = 0xffff
4114 }
4115 zVRIa(op, uint32(p.To.Reg), i2, m3, asm)
4116
4117 case 110:
4118 op, m4, _ := vop(p.As)
4119 i2 := uint32(c.vregoff(&p.From))
4120 i3 := uint32(c.vregoff(p.GetFrom3()))
4121 zVRIb(op, uint32(p.To.Reg), i2, i3, m4, asm)
4122
4123 case 111:
4124 op, m4, _ := vop(p.As)
4125 i2 := uint32(c.vregoff(&p.From))
4126 zVRIc(op, uint32(p.To.Reg), uint32(p.Reg), i2, m4, asm)
4127
4128 case 112:
4129 op, m5, _ := vop(p.As)
4130 i4 := uint32(c.vregoff(&p.From))
4131 zVRId(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), i4, m5, asm)
4132
4133 case 113:
4134 op, m4, _ := vop(p.As)
4135 m5 := singleElementMask(p.As)
4136 i3 := uint32(c.vregoff(&p.From))
4137 zVRIe(op, uint32(p.To.Reg), uint32(p.Reg), i3, m5, m4, asm)
4138
4139 case 114:
4140 op, m3, m5 := vop(p.As)
4141 m4 := singleElementMask(p.As)
4142 zVRRa(op, uint32(p.To.Reg), uint32(p.From.Reg), m5, m4, m3, asm)
4143
4144 case 115:
4145 op, m3, m5 := vop(p.As)
4146 m4 := singleElementMask(p.As)
4147 zVRRa(op, uint32(p.From.Reg), uint32(p.To.Reg), m5, m4, m3, asm)
4148
4149 case 117:
4150 op, m4, m5 := vop(p.As)
4151 zVRRb(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), m5, m4, asm)
4152
4153 case 118:
4154 op, m4, m6 := vop(p.As)
4155 m5 := singleElementMask(p.As)
4156 v3 := p.Reg
4157 if v3 == 0 {
4158 v3 = p.To.Reg
4159 }
4160 zVRRc(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(v3), m6, m5, m4, asm)
4161
4162 case 119:
4163 op, m4, m6 := vop(p.As)
4164 m5 := singleElementMask(p.As)
4165 v2 := p.Reg
4166 if v2 == 0 {
4167 v2 = p.To.Reg
4168 }
4169 zVRRc(op, uint32(p.To.Reg), uint32(v2), uint32(p.From.Reg), m6, m5, m4, asm)
4170
4171 case 120:
4172 op, m6, _ := vop(p.As)
4173 m5 := singleElementMask(p.As)
4174 v1 := uint32(p.To.Reg)
4175 v2 := uint32(p.From.Reg)
4176 v3 := uint32(p.Reg)
4177 v4 := uint32(p.GetFrom3().Reg)
4178 zVRRd(op, v1, v2, v3, m6, m5, v4, asm)
4179
4180 case 121:
4181 op, m6, _ := vop(p.As)
4182 m5 := singleElementMask(p.As)
4183 v1 := uint32(p.To.Reg)
4184 v2 := uint32(p.From.Reg)
4185 v3 := uint32(p.Reg)
4186 v4 := uint32(p.GetFrom3().Reg)
4187 zVRRe(op, v1, v2, v3, m6, m5, v4, asm)
4188
4189 case 122:
4190 op, _, _ := vop(p.As)
4191 zVRRf(op, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), asm)
4192
4193 case 123:
4194 op, _, _ := vop(p.As)
4195 m4 := c.regoff(&p.From)
4196 zVRRc(op, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), 0, 0, uint32(m4), asm)
4197 }
4198 }
4199
4200 func (c *ctxtz) vregoff(a *obj.Addr) int64 {
4201 c.instoffset = 0
4202 if a != nil {
4203 c.aclass(a)
4204 }
4205 return c.instoffset
4206 }
4207
4208 func (c *ctxtz) regoff(a *obj.Addr) int32 {
4209 return int32(c.vregoff(a))
4210 }
4211
4212
4213 func (c *ctxtz) zopload(a obj.As) uint32 {
4214 switch a {
4215
4216 case AMOVD:
4217 return op_LG
4218 case AMOVW:
4219 return op_LGF
4220 case AMOVWZ:
4221 return op_LLGF
4222 case AMOVH:
4223 return op_LGH
4224 case AMOVHZ:
4225 return op_LLGH
4226 case AMOVB:
4227 return op_LGB
4228 case AMOVBZ:
4229 return op_LLGC
4230
4231
4232 case AFMOVD:
4233 return op_LDY
4234 case AFMOVS:
4235 return op_LEY
4236
4237
4238 case AMOVDBR:
4239 return op_LRVG
4240 case AMOVWBR:
4241 return op_LRV
4242 case AMOVHBR:
4243 return op_LRVH
4244 }
4245
4246 c.ctxt.Diag("unknown store opcode %v", a)
4247 return 0
4248 }
4249
4250
4251 func (c *ctxtz) zopstore(a obj.As) uint32 {
4252 switch a {
4253
4254 case AMOVD:
4255 return op_STG
4256 case AMOVW, AMOVWZ:
4257 return op_STY
4258 case AMOVH, AMOVHZ:
4259 return op_STHY
4260 case AMOVB, AMOVBZ:
4261 return op_STCY
4262
4263
4264 case AFMOVD:
4265 return op_STDY
4266 case AFMOVS:
4267 return op_STEY
4268
4269
4270 case AMOVDBR:
4271 return op_STRVG
4272 case AMOVWBR:
4273 return op_STRV
4274 case AMOVHBR:
4275 return op_STRVH
4276 }
4277
4278 c.ctxt.Diag("unknown store opcode %v", a)
4279 return 0
4280 }
4281
4282
4283 func (c *ctxtz) zoprre(a obj.As) uint32 {
4284 switch a {
4285 case ACMP:
4286 return op_CGR
4287 case ACMPU:
4288 return op_CLGR
4289 case AFCMPO:
4290 return op_KDBR
4291 case AFCMPU:
4292 return op_CDBR
4293 case ACEBR:
4294 return op_CEBR
4295 }
4296 c.ctxt.Diag("unknown rre opcode %v", a)
4297 return 0
4298 }
4299
4300
4301 func (c *ctxtz) zoprr(a obj.As) uint32 {
4302 switch a {
4303 case ACMPW:
4304 return op_CR
4305 case ACMPWU:
4306 return op_CLR
4307 }
4308 c.ctxt.Diag("unknown rr opcode %v", a)
4309 return 0
4310 }
4311
4312
4313 func (c *ctxtz) zopril(a obj.As) uint32 {
4314 switch a {
4315 case ACMP:
4316 return op_CGFI
4317 case ACMPU:
4318 return op_CLGFI
4319 case ACMPW:
4320 return op_CFI
4321 case ACMPWU:
4322 return op_CLFI
4323 }
4324 c.ctxt.Diag("unknown ril opcode %v", a)
4325 return 0
4326 }
4327
4328
4329 const (
4330 sizeE = 2
4331 sizeI = 2
4332 sizeIE = 4
4333 sizeMII = 6
4334 sizeRI = 4
4335 sizeRI1 = 4
4336 sizeRI2 = 4
4337 sizeRI3 = 4
4338 sizeRIE = 6
4339 sizeRIE1 = 6
4340 sizeRIE2 = 6
4341 sizeRIE3 = 6
4342 sizeRIE4 = 6
4343 sizeRIE5 = 6
4344 sizeRIE6 = 6
4345 sizeRIL = 6
4346 sizeRIL1 = 6
4347 sizeRIL2 = 6
4348 sizeRIL3 = 6
4349 sizeRIS = 6
4350 sizeRR = 2
4351 sizeRRD = 4
4352 sizeRRE = 4
4353 sizeRRF = 4
4354 sizeRRF1 = 4
4355 sizeRRF2 = 4
4356 sizeRRF3 = 4
4357 sizeRRF4 = 4
4358 sizeRRF5 = 4
4359 sizeRRR = 2
4360 sizeRRS = 6
4361 sizeRS = 4
4362 sizeRS1 = 4
4363 sizeRS2 = 4
4364 sizeRSI = 4
4365 sizeRSL = 6
4366 sizeRSY = 6
4367 sizeRSY1 = 6
4368 sizeRSY2 = 6
4369 sizeRX = 4
4370 sizeRX1 = 4
4371 sizeRX2 = 4
4372 sizeRXE = 6
4373 sizeRXF = 6
4374 sizeRXY = 6
4375 sizeRXY1 = 6
4376 sizeRXY2 = 6
4377 sizeS = 4
4378 sizeSI = 4
4379 sizeSIL = 6
4380 sizeSIY = 6
4381 sizeSMI = 6
4382 sizeSS = 6
4383 sizeSS1 = 6
4384 sizeSS2 = 6
4385 sizeSS3 = 6
4386 sizeSS4 = 6
4387 sizeSS5 = 6
4388 sizeSS6 = 6
4389 sizeSSE = 6
4390 sizeSSF = 6
4391 )
4392
4393
4394 type form int
4395
4396 const (
4397 _a form = iota
4398 _b
4399 _c
4400 _d
4401 _e
4402 _f
4403 )
4404
4405 func zE(op uint32, asm *[]byte) {
4406 *asm = append(*asm, uint8(op>>8), uint8(op))
4407 }
4408
4409 func zI(op, i1 uint32, asm *[]byte) {
4410 *asm = append(*asm, uint8(op>>8), uint8(i1))
4411 }
4412
4413 func zMII(op, m1, ri2, ri3 uint32, asm *[]byte) {
4414 *asm = append(*asm,
4415 uint8(op>>8),
4416 (uint8(m1)<<4)|uint8((ri2>>8)&0x0F),
4417 uint8(ri2),
4418 uint8(ri3>>16),
4419 uint8(ri3>>8),
4420 uint8(ri3))
4421 }
4422
4423 func zRI(op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4424 *asm = append(*asm,
4425 uint8(op>>8),
4426 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4427 uint8(i2_ri2>>8),
4428 uint8(i2_ri2))
4429 }
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442 func zRIE(f form, op, r1, r2_m3_r3, i2_ri4_ri2, i3, i4, m3, i2_i5 uint32, asm *[]byte) {
4443 *asm = append(*asm, uint8(op>>8), uint8(r1)<<4|uint8(r2_m3_r3&0x0F))
4444
4445 switch f {
4446 default:
4447 *asm = append(*asm, uint8(i2_ri4_ri2>>8), uint8(i2_ri4_ri2))
4448 case _f:
4449 *asm = append(*asm, uint8(i3), uint8(i4))
4450 }
4451
4452 switch f {
4453 case _a, _b:
4454 *asm = append(*asm, uint8(m3)<<4)
4455 default:
4456 *asm = append(*asm, uint8(i2_i5))
4457 }
4458
4459 *asm = append(*asm, uint8(op))
4460 }
4461
4462 func zRIL(f form, op, r1_m1, i2_ri2 uint32, asm *[]byte) {
4463 if f == _a || f == _b {
4464 r1_m1 = r1_m1 - obj.RBaseS390X
4465 }
4466 *asm = append(*asm,
4467 uint8(op>>8),
4468 (uint8(r1_m1)<<4)|(uint8(op)&0x0F),
4469 uint8(i2_ri2>>24),
4470 uint8(i2_ri2>>16),
4471 uint8(i2_ri2>>8),
4472 uint8(i2_ri2))
4473 }
4474
4475 func zRIS(op, r1, m3, b4, d4, i2 uint32, asm *[]byte) {
4476 *asm = append(*asm,
4477 uint8(op>>8),
4478 (uint8(r1)<<4)|uint8(m3&0x0F),
4479 (uint8(b4)<<4)|(uint8(d4>>8)&0x0F),
4480 uint8(d4),
4481 uint8(i2),
4482 uint8(op))
4483 }
4484
4485 func zRR(op, r1, r2 uint32, asm *[]byte) {
4486 *asm = append(*asm, uint8(op>>8), (uint8(r1)<<4)|uint8(r2&0x0F))
4487 }
4488
4489 func zRRD(op, r1, r3, r2 uint32, asm *[]byte) {
4490 *asm = append(*asm,
4491 uint8(op>>8),
4492 uint8(op),
4493 uint8(r1)<<4,
4494 (uint8(r3)<<4)|uint8(r2&0x0F))
4495 }
4496
4497 func zRRE(op, r1, r2 uint32, asm *[]byte) {
4498 *asm = append(*asm,
4499 uint8(op>>8),
4500 uint8(op),
4501 0,
4502 (uint8(r1)<<4)|uint8(r2&0x0F))
4503 }
4504
4505 func zRRF(op, r3_m3, m4, r1, r2 uint32, asm *[]byte) {
4506 *asm = append(*asm,
4507 uint8(op>>8),
4508 uint8(op),
4509 (uint8(r3_m3)<<4)|uint8(m4&0x0F),
4510 (uint8(r1)<<4)|uint8(r2&0x0F))
4511 }
4512
4513 func zRRS(op, r1, r2, b4, d4, m3 uint32, asm *[]byte) {
4514 *asm = append(*asm,
4515 uint8(op>>8),
4516 (uint8(r1)<<4)|uint8(r2&0x0F),
4517 (uint8(b4)<<4)|uint8((d4>>8)&0x0F),
4518 uint8(d4),
4519 uint8(m3)<<4,
4520 uint8(op))
4521 }
4522
4523 func zRS(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4524 *asm = append(*asm,
4525 uint8(op>>8),
4526 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4527 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4528 uint8(d2))
4529 }
4530
4531 func zRSI(op, r1, r3, ri2 uint32, asm *[]byte) {
4532 *asm = append(*asm,
4533 uint8(op>>8),
4534 (uint8(r1)<<4)|uint8(r3&0x0F),
4535 uint8(ri2>>8),
4536 uint8(ri2))
4537 }
4538
4539 func zRSL(op, l1, b2, d2 uint32, asm *[]byte) {
4540 *asm = append(*asm,
4541 uint8(op>>8),
4542 uint8(l1),
4543 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4544 uint8(d2),
4545 uint8(op))
4546 }
4547
4548 func zRSY(op, r1, r3_m3, b2, d2 uint32, asm *[]byte) {
4549 dl2 := uint16(d2) & 0x0FFF
4550 *asm = append(*asm,
4551 uint8(op>>8),
4552 (uint8(r1)<<4)|uint8(r3_m3&0x0F),
4553 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4554 uint8(dl2),
4555 uint8(d2>>12),
4556 uint8(op))
4557 }
4558
4559 func zRX(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4560 *asm = append(*asm,
4561 uint8(op>>8),
4562 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4563 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4564 uint8(d2))
4565 }
4566
4567 func zRXE(op, r1, x2, b2, d2, m3 uint32, asm *[]byte) {
4568 *asm = append(*asm,
4569 uint8(op>>8),
4570 (uint8(r1)<<4)|uint8(x2&0x0F),
4571 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4572 uint8(d2),
4573 uint8(m3)<<4,
4574 uint8(op))
4575 }
4576
4577 func zRXF(op, r3, x2, b2, d2, m1 uint32, asm *[]byte) {
4578 *asm = append(*asm,
4579 uint8(op>>8),
4580 (uint8(r3)<<4)|uint8(x2&0x0F),
4581 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4582 uint8(d2),
4583 uint8(m1)<<4,
4584 uint8(op))
4585 }
4586
4587 func zRXY(op, r1_m1, x2, b2, d2 uint32, asm *[]byte) {
4588 dl2 := uint16(d2) & 0x0FFF
4589 *asm = append(*asm,
4590 uint8(op>>8),
4591 (uint8(r1_m1)<<4)|uint8(x2&0x0F),
4592 (uint8(b2)<<4)|(uint8(dl2>>8)&0x0F),
4593 uint8(dl2),
4594 uint8(d2>>12),
4595 uint8(op))
4596 }
4597
4598 func zS(op, b2, d2 uint32, asm *[]byte) {
4599 *asm = append(*asm,
4600 uint8(op>>8),
4601 uint8(op),
4602 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4603 uint8(d2))
4604 }
4605
4606 func zSI(op, i2, b1, d1 uint32, asm *[]byte) {
4607 *asm = append(*asm,
4608 uint8(op>>8),
4609 uint8(i2),
4610 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4611 uint8(d1))
4612 }
4613
4614 func zSIL(op, b1, d1, i2 uint32, asm *[]byte) {
4615 *asm = append(*asm,
4616 uint8(op>>8),
4617 uint8(op),
4618 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4619 uint8(d1),
4620 uint8(i2>>8),
4621 uint8(i2))
4622 }
4623
4624 func zSIY(op, i2, b1, d1 uint32, asm *[]byte) {
4625 dl1 := uint16(d1) & 0x0FFF
4626 *asm = append(*asm,
4627 uint8(op>>8),
4628 uint8(i2),
4629 (uint8(b1)<<4)|(uint8(dl1>>8)&0x0F),
4630 uint8(dl1),
4631 uint8(d1>>12),
4632 uint8(op))
4633 }
4634
4635 func zSMI(op, m1, b3, d3, ri2 uint32, asm *[]byte) {
4636 *asm = append(*asm,
4637 uint8(op>>8),
4638 uint8(m1)<<4,
4639 (uint8(b3)<<4)|uint8((d3>>8)&0x0F),
4640 uint8(d3),
4641 uint8(ri2>>8),
4642 uint8(ri2))
4643 }
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655 func zSS(f form, op, l1_r1, l2_i3_r3, b1_b2, d1_d2, b2_b4, d2_d4 uint32, asm *[]byte) {
4656 *asm = append(*asm, uint8(op>>8))
4657
4658 switch f {
4659 case _a:
4660 *asm = append(*asm, uint8(l1_r1))
4661 case _b, _c, _d, _e:
4662 *asm = append(*asm, (uint8(l1_r1)<<4)|uint8(l2_i3_r3&0x0F))
4663 case _f:
4664 *asm = append(*asm, uint8(l2_i3_r3))
4665 }
4666
4667 *asm = append(*asm,
4668 (uint8(b1_b2)<<4)|uint8((d1_d2>>8)&0x0F),
4669 uint8(d1_d2),
4670 (uint8(b2_b4)<<4)|uint8((d2_d4>>8)&0x0F),
4671 uint8(d2_d4))
4672 }
4673
4674 func zSSE(op, b1, d1, b2, d2 uint32, asm *[]byte) {
4675 *asm = append(*asm,
4676 uint8(op>>8),
4677 uint8(op),
4678 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4679 uint8(d1),
4680 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4681 uint8(d2))
4682 }
4683
4684 func zSSF(op, r3, b1, d1, b2, d2 uint32, asm *[]byte) {
4685 *asm = append(*asm,
4686 uint8(op>>8),
4687 (uint8(r3)<<4)|(uint8(op)&0x0F),
4688 (uint8(b1)<<4)|uint8((d1>>8)&0x0F),
4689 uint8(d1),
4690 (uint8(b2)<<4)|uint8((d2>>8)&0x0F),
4691 uint8(d2))
4692 }
4693
4694 func rxb(va, vb, vc, vd uint32) uint8 {
4695 mask := uint8(0)
4696 if va >= REG_V16 && va <= REG_V31 {
4697 mask |= 0x8
4698 }
4699 if vb >= REG_V16 && vb <= REG_V31 {
4700 mask |= 0x4
4701 }
4702 if vc >= REG_V16 && vc <= REG_V31 {
4703 mask |= 0x2
4704 }
4705 if vd >= REG_V16 && vd <= REG_V31 {
4706 mask |= 0x1
4707 }
4708 return mask
4709 }
4710
4711 func zVRX(op, v1, x2, b2, d2, m3 uint32, asm *[]byte) {
4712 *asm = append(*asm,
4713 uint8(op>>8),
4714 (uint8(v1)<<4)|(uint8(x2)&0xf),
4715 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4716 uint8(d2),
4717 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4718 uint8(op))
4719 }
4720
4721 func zVRV(op, v1, v2, b2, d2, m3 uint32, asm *[]byte) {
4722 *asm = append(*asm,
4723 uint8(op>>8),
4724 (uint8(v1)<<4)|(uint8(v2)&0xf),
4725 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4726 uint8(d2),
4727 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4728 uint8(op))
4729 }
4730
4731 func zVRS(op, v1, v3_r3, b2, d2, m4 uint32, asm *[]byte) {
4732 *asm = append(*asm,
4733 uint8(op>>8),
4734 (uint8(v1)<<4)|(uint8(v3_r3)&0xf),
4735 (uint8(b2)<<4)|(uint8(d2>>8)&0xf),
4736 uint8(d2),
4737 (uint8(m4)<<4)|rxb(v1, v3_r3, 0, 0),
4738 uint8(op))
4739 }
4740
4741 func zVRRa(op, v1, v2, m5, m4, m3 uint32, asm *[]byte) {
4742 *asm = append(*asm,
4743 uint8(op>>8),
4744 (uint8(v1)<<4)|(uint8(v2)&0xf),
4745 0,
4746 (uint8(m5)<<4)|(uint8(m4)&0xf),
4747 (uint8(m3)<<4)|rxb(v1, v2, 0, 0),
4748 uint8(op))
4749 }
4750
4751 func zVRRb(op, v1, v2, v3, m5, m4 uint32, asm *[]byte) {
4752 *asm = append(*asm,
4753 uint8(op>>8),
4754 (uint8(v1)<<4)|(uint8(v2)&0xf),
4755 uint8(v3)<<4,
4756 uint8(m5)<<4,
4757 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4758 uint8(op))
4759 }
4760
4761 func zVRRc(op, v1, v2, v3, m6, m5, m4 uint32, asm *[]byte) {
4762 *asm = append(*asm,
4763 uint8(op>>8),
4764 (uint8(v1)<<4)|(uint8(v2)&0xf),
4765 uint8(v3)<<4,
4766 (uint8(m6)<<4)|(uint8(m5)&0xf),
4767 (uint8(m4)<<4)|rxb(v1, v2, v3, 0),
4768 uint8(op))
4769 }
4770
4771 func zVRRd(op, v1, v2, v3, m5, m6, v4 uint32, asm *[]byte) {
4772 *asm = append(*asm,
4773 uint8(op>>8),
4774 (uint8(v1)<<4)|(uint8(v2)&0xf),
4775 (uint8(v3)<<4)|(uint8(m5)&0xf),
4776 uint8(m6)<<4,
4777 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4778 uint8(op))
4779 }
4780
4781 func zVRRe(op, v1, v2, v3, m6, m5, v4 uint32, asm *[]byte) {
4782 *asm = append(*asm,
4783 uint8(op>>8),
4784 (uint8(v1)<<4)|(uint8(v2)&0xf),
4785 (uint8(v3)<<4)|(uint8(m6)&0xf),
4786 uint8(m5),
4787 (uint8(v4)<<4)|rxb(v1, v2, v3, v4),
4788 uint8(op))
4789 }
4790
4791 func zVRRf(op, v1, r2, r3 uint32, asm *[]byte) {
4792 *asm = append(*asm,
4793 uint8(op>>8),
4794 (uint8(v1)<<4)|(uint8(r2)&0xf),
4795 uint8(r3)<<4,
4796 0,
4797 rxb(v1, 0, 0, 0),
4798 uint8(op))
4799 }
4800
4801 func zVRIa(op, v1, i2, m3 uint32, asm *[]byte) {
4802 *asm = append(*asm,
4803 uint8(op>>8),
4804 uint8(v1)<<4,
4805 uint8(i2>>8),
4806 uint8(i2),
4807 (uint8(m3)<<4)|rxb(v1, 0, 0, 0),
4808 uint8(op))
4809 }
4810
4811 func zVRIb(op, v1, i2, i3, m4 uint32, asm *[]byte) {
4812 *asm = append(*asm,
4813 uint8(op>>8),
4814 uint8(v1)<<4,
4815 uint8(i2),
4816 uint8(i3),
4817 (uint8(m4)<<4)|rxb(v1, 0, 0, 0),
4818 uint8(op))
4819 }
4820
4821 func zVRIc(op, v1, v3, i2, m4 uint32, asm *[]byte) {
4822 *asm = append(*asm,
4823 uint8(op>>8),
4824 (uint8(v1)<<4)|(uint8(v3)&0xf),
4825 uint8(i2>>8),
4826 uint8(i2),
4827 (uint8(m4)<<4)|rxb(v1, v3, 0, 0),
4828 uint8(op))
4829 }
4830
4831 func zVRId(op, v1, v2, v3, i4, m5 uint32, asm *[]byte) {
4832 *asm = append(*asm,
4833 uint8(op>>8),
4834 (uint8(v1)<<4)|(uint8(v2)&0xf),
4835 uint8(v3)<<4,
4836 uint8(i4),
4837 (uint8(m5)<<4)|rxb(v1, v2, v3, 0),
4838 uint8(op))
4839 }
4840
4841 func zVRIe(op, v1, v2, i3, m5, m4 uint32, asm *[]byte) {
4842 *asm = append(*asm,
4843 uint8(op>>8),
4844 (uint8(v1)<<4)|(uint8(v2)&0xf),
4845 uint8(i3>>4),
4846 (uint8(i3)<<4)|(uint8(m5)&0xf),
4847 (uint8(m4)<<4)|rxb(v1, v2, 0, 0),
4848 uint8(op))
4849 }
4850
View as plain text