Source file src/pkg/cmd/internal/obj/ppc64/asm9.go

     1	// cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova.
     2	//
     3	//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4	//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5	//	Portions Copyright © 1997-1999 Vita Nuova Limited
     6	//	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7	//	Portions Copyright © 2004,2006 Bruce Ellis
     8	//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9	//	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10	//	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11	//
    12	// Permission is hereby granted, free of charge, to any person obtaining a copy
    13	// of this software and associated documentation files (the "Software"), to deal
    14	// in the Software without restriction, including without limitation the rights
    15	// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16	// copies of the Software, and to permit persons to whom the Software is
    17	// furnished to do so, subject to the following conditions:
    18	//
    19	// The above copyright notice and this permission notice shall be included in
    20	// all copies or substantial portions of the Software.
    21	//
    22	// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23	// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24	// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25	// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26	// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27	// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28	// THE SOFTWARE.
    29	
    30	package ppc64
    31	
    32	import (
    33		"cmd/internal/obj"
    34		"cmd/internal/objabi"
    35		"encoding/binary"
    36		"fmt"
    37		"log"
    38		"math"
    39		"sort"
    40	)
    41	
    42	// ctxt9 holds state while assembling a single function.
    43	// Each function gets a fresh ctxt9.
    44	// This allows for multiple functions to be safely concurrently assembled.
    45	type ctxt9 struct {
    46		ctxt       *obj.Link
    47		newprog    obj.ProgAlloc
    48		cursym     *obj.LSym
    49		autosize   int32
    50		instoffset int64
    51		pc         int64
    52	}
    53	
    54	// Instruction layout.
    55	
    56	const (
    57		funcAlign = 16
    58	)
    59	
    60	const (
    61		r0iszero = 1
    62	)
    63	
    64	type Optab struct {
    65		as    obj.As // Opcode
    66		a1    uint8
    67		a2    uint8
    68		a3    uint8
    69		a4    uint8
    70		type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r
    71		size  int8
    72		param int16
    73	}
    74	
    75	// This optab contains a list of opcodes with the operand
    76	// combinations that are implemented. Not all opcodes are in this
    77	// table, but are added later in buildop by calling opset for those
    78	// opcodes which allow the same operand combinations as an opcode
    79	// already in the table.
    80	//
    81	// The type field in the Optabl identifies the case in asmout where
    82	// the instruction word is assembled.
    83	var optab = []Optab{
    84		{obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
    85		{obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
    86		{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0},
    87		{obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0},
    88		/* move register */
    89		{AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0},
    90		{AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
    91		{AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
    92		{AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0},
    93		{AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0},
    94		{AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
    95		{AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
    96		{AADD, C_SCON, C_REG, C_NONE, C_REG, 4, 4, 0},
    97		{AADD, C_SCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
    98		{AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
    99		{AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
   100		{AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0},
   101		{AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0},
   102		{AADD, C_ANDCON, C_REG, C_NONE, C_REG, 22, 8, 0},
   103		{AADD, C_ANDCON, C_NONE, C_NONE, C_REG, 22, 8, 0},
   104		{AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
   105		{AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
   106		{AADDIS, C_ADDCON, C_REG, C_NONE, C_REG, 20, 4, 0},
   107		{AADDIS, C_ADDCON, C_NONE, C_NONE, C_REG, 20, 4, 0},
   108		{AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
   109		{AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
   110		{AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
   111		{AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
   112		{AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
   113		{AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
   114		{AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */
   115		{AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   116		{AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
   117		{AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   118		{AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
   119		{AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
   120		{AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
   121		{AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
   122		{AANDCC, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0},
   123		{AANDCC, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0},
   124		{AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
   125		{AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
   126		{AANDISCC, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
   127		{AANDISCC, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0},
   128		{AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0},
   129		{AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
   130		{AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
   131		{AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
   132		{AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0},
   133		{AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0},
   134		{AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0},
   135		{AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0},
   136		{ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0},
   137		{ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
   138		{ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0},
   139		{ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0},
   140		{AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */
   141		{AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   142		{AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0},
   143		{AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0},
   144		{AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
   145		{AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0},
   146		{AOR, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0},
   147		{AOR, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0},
   148		{AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0},
   149		{AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0},
   150		{AORIS, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0},
   151		{AORIS, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0},
   152		{ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */
   153		{ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0},
   154		{ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */
   155		{ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0},
   156		{ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   157		{ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
   158		{ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   159		{ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
   160		{ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0},
   161		{ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0},
   162		{ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0},
   163		{ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0},
   164		{ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   165		{ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
   166		{ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
   167		{ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
   168		{ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0},
   169		{ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0},
   170		{ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0},
   171		{ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0},
   172		{ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0},
   173		{ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0},
   174		{ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0},
   175		{ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
   176		{ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0},
   177		{ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
   178		{ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0},
   179		{ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0},
   180		{ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0},
   181		{AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0},
   182		{AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0},
   183		{AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
   184		{AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0},
   185		{AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0},
   186		{AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0},
   187		{AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0},
   188		{AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0},
   189	
   190		/* store, short offset */
   191		{AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   192		{AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   193		{AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   194		{AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   195		{AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   196		{AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   197		{AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO},
   198		{AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   199		{AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   200		{AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   201		{AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   202		{AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   203		{AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   204		{AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   205		{AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   206		{AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   207		{AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   208		{AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   209		{AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   210		{AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   211		{AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   212		{AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   213		{AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   214		{AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   215	
   216		/* load, short offset */
   217		{AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
   218		{AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
   219		{AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
   220		{AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
   221		{AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO},
   222		{AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
   223		{AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO},
   224		{AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
   225		{AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
   226		{AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
   227		{AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB},
   228		{AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB},
   229		{AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
   230		{AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
   231		{AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
   232		{AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP},
   233		{AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP},
   234		{AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
   235		{AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
   236		{AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
   237		{AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
   238		{AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO},
   239		{AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
   240		{AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO},
   241	
   242		/* store, long offset */
   243		{AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   244		{AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   245		{AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   246		{AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   247		{AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   248		{AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   249		{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   250		{AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   251		{AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   252		{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   253		{AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   254		{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   255		{AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   256		{AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   257		{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   258		{AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   259		{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   260		{AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   261		{AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   262		{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   263	
   264		/* load, long offset */
   265		{AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
   266		{AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
   267		{AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
   268		{AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB},
   269		{AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB},
   270		{AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
   271		{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
   272		{AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
   273		{AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP},
   274		{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP},
   275		{AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
   276		{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
   277		{AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
   278		{AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO},
   279		{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO},
   280		{AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
   281		{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
   282		{AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
   283		{AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0},
   284		{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0},
   285	
   286		{AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0},
   287		{AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0},
   288	
   289		{AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0},
   290		{AMOVD, C_TOCADDR, C_NONE, C_NONE, C_REG, 95, 8, 0},
   291	
   292		/* load constant */
   293		{AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB},
   294		{AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
   295		{AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
   296		{AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
   297		{AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   298		{AMOVD, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   299		{AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
   300		{AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
   301		{AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
   302		{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
   303		{AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   304		{AMOVW, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   305		{AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */
   306		{AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP},
   307		{AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB},
   308		{AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP},
   309		{AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   310		{AMOVWZ, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   311	
   312		/* load unsigned/long constants (TO DO: check) */
   313		{AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   314		{AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
   315		{AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   316		{AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
   317		{AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO},
   318		{AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0},
   319		{AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
   320		{AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
   321		{AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
   322		{AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
   323		{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0},
   324		{ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0},
   325		{ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0},
   326		{ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
   327		{ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0},
   328		{ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0},
   329		{ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0},
   330		{ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0},
   331		{ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0},
   332		{ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0},
   333		{ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0},
   334		{ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0},
   335		{ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
   336		{ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0},
   337		{ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0},
   338		{ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0},
   339		{ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0},
   340		{ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0},
   341		{AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB},
   342		{AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP},
   343		{AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO},
   344		{AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB},
   345		{AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP},
   346		{AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO},
   347		{AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 24, 4, 0},
   348		{AFMOVD, C_ADDCON, C_NONE, C_NONE, C_FREG, 24, 8, 0},
   349		{AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0},
   350		{AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB},
   351		{AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP},
   352		{AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO},
   353		{AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB},
   354		{AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP},
   355		{AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO},
   356		{AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0},
   357		{AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
   358		{AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
   359		{AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
   360		{AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
   361		{AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0},
   362		{AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0},
   363		{ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
   364		{AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0},
   365		{ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
   366		{ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0},
   367		{AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
   368		{AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0},
   369		{AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0},
   370		{AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0},
   371		{AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0},
   372		{ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0},
   373		{ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0},
   374		{AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0},
   375		{AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0},
   376		{AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0},
   377		{AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0},
   378		{AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0},
   379		{AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0},
   380		{AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0},
   381		{AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0},
   382		{AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0},
   383		{AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0},
   384		{AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0},
   385		{AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0},
   386		{AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0},
   387		{AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0},  /* mfmsr */
   388		{AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0},  /* mtmsrd */
   389		{AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */
   390	
   391		/* Other ISA 2.05+ instructions */
   392		{APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */
   393		{ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0},     /* compare byte, x-form */
   394		{ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0},  /* compare equal byte, x-form, ISA 3.0 */
   395		{ACMPEQB, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
   396		{AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0},  /* floating test for sw divide, x-form */
   397		{AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */
   398		{ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0},     /* copy/paste facility, x-form */
   399		{ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0},    /* deliver random number, x-form */
   400		{ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},   /* load doubleword monitored, x-form */
   401		{AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0},     /* multiply-add high/low doubleword, va-form */
   402		{AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0},     /* add extended using alternate carry, z23-form */
   403	
   404		/* Vector instructions */
   405	
   406		/* Vector load */
   407		{ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */
   408	
   409		/* Vector store */
   410		{ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */
   411	
   412		/* Vector logical */
   413		{AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */
   414		{AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},  /* vector or, vx-form */
   415	
   416		/* Vector add */
   417		{AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */
   418		{AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */
   419		{AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */
   420		{AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */
   421		{AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0},  /* vector add extended, va-form */
   422	
   423		/* Vector subtract */
   424		{AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */
   425		{AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */
   426		{AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */
   427		{AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */
   428		{AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0},  /* vector subtract extended, va-form */
   429	
   430		/* Vector multiply */
   431		{AVMULESB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 9},  /* vector multiply, vx-form */
   432		{AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},   /* vector polynomial multiply & sum, vx-form */
   433		{AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */
   434	
   435		/* Vector rotate */
   436		{AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */
   437	
   438		/* Vector shift */
   439		{AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},     /* vector shift, vx-form */
   440		{AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},    /* vector shift algebraic, vx-form */
   441		{AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */
   442	
   443		/* Vector count */
   444		{AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0},    /* vector count leading zeros, vx-form */
   445		{AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */
   446	
   447		/* Vector compare */
   448		{AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},   /* vector compare equal, vc-form */
   449		{AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},   /* vector compare greater than, vc-form */
   450		{AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */
   451	
   452		/* Vector permute */
   453		{AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */
   454	
   455		/* Vector bit permute */
   456		{AVBPERMQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector bit permute, vx-form */
   457	
   458		/* Vector select */
   459		{AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */
   460	
   461		/* Vector splat */
   462		{AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */
   463		{AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0},
   464		{AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */
   465		{AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0},
   466	
   467		/* Vector AES */
   468		{AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0},  /* vector AES cipher, vx-form */
   469		{AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */
   470		{AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0},  /* vector AES subbytes, vx-form */
   471	
   472		/* Vector SHA */
   473		{AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */
   474	
   475		/* VSX vector load */
   476		{ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */
   477	
   478		/* VSX vector store */
   479		{ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */
   480	
   481		/* VSX scalar load */
   482		{ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */
   483	
   484		/* VSX scalar store */
   485		{ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */
   486	
   487		/* VSX scalar as integer load */
   488		{ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */
   489	
   490		/* VSX scalar store as integer */
   491		{ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */
   492	
   493		/* VSX move from VSR */
   494		{AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */
   495		{AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
   496		{AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0},
   497	
   498		/* VSX move to VSR */
   499		{AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */
   500		{AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0},
   501		{AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0},
   502		{AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0},
   503	
   504		/* VSX logical */
   505		{AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */
   506		{AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0},  /* vsx or, xx3-form */
   507	
   508		/* VSX select */
   509		{AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */
   510	
   511		/* VSX merge */
   512		{AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */
   513	
   514		/* VSX splat */
   515		{AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */
   516	
   517		/* VSX permute */
   518		{AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */
   519	
   520		/* VSX shift */
   521		{AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */
   522	
   523		/* VSX scalar FP-FP conversion */
   524		{AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */
   525	
   526		/* VSX vector FP-FP conversion */
   527		{AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */
   528	
   529		/* VSX scalar FP-integer conversion */
   530		{AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */
   531	
   532		/* VSX scalar integer-FP conversion */
   533		{AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */
   534	
   535		/* VSX vector FP-integer conversion */
   536		{AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */
   537	
   538		/* VSX vector integer-FP conversion */
   539		{AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */
   540	
   541		/* 64-bit special registers */
   542		{AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
   543		{AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0},
   544		{AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
   545		{AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
   546		{AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
   547		{AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0},
   548		{AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0},
   549		{AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
   550	
   551		/* 32-bit special registers (gloss over sign-extension or not?) */
   552		{AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
   553		{AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
   554		{AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
   555		{AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
   556		{AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
   557		{AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0},
   558		{AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0},
   559		{AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0},
   560		{AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0},
   561		{AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0},
   562		{AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0},
   563		{AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0},
   564		{AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
   565		{AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0},
   566		{AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0},
   567		{AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
   568		{AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
   569		{AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0},
   570		{ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
   571		{ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
   572		{ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0},
   573		{ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0},
   574		{ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0},
   575		{ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0},
   576		{ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0},
   577		{ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0},
   578		{AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0},
   579		{AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0},
   580		{ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0},
   581		{ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0},
   582		{ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0},
   583		{ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0},
   584		{ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0},
   585		{ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0},
   586		{AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0},
   587		{AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0},
   588		{AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
   589		{AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
   590		{ALDAR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
   591		{ALDAR, C_ZOREG, C_NONE, C_ANDCON, C_REG, 45, 4, 0},
   592		{AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0},
   593		{ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0},
   594		{ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0},
   595		{ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
   596		{ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0},
   597		{ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0},
   598		{ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0},
   599		{ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0},
   600		{ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0},
   601		{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0},
   602		{obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0},
   603		{obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0},
   604		{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0},
   605		{obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
   606		{obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL
   607		{obj.APCALIGN, C_LCON, C_NONE, C_NONE, C_NONE, 0, 0, 0},   // align code
   608	
   609		{obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0},
   610	}
   611	
   612	var oprange [ALAST & obj.AMask][]Optab
   613	
   614	var xcmp [C_NCLASS][C_NCLASS]bool
   615	
   616	// padding bytes to add to align code as requested
   617	func addpad(pc, a int64, ctxt *obj.Link) int {
   618		switch a {
   619		case 8:
   620			if pc%8 != 0 {
   621				return 4
   622			}
   623		case 16:
   624			switch pc % 16 {
   625			// When currently aligned to 4, avoid 3 NOPs and set to
   626			// 8 byte alignment which should still help.
   627			case 4, 12:
   628				return 4
   629			case 8:
   630				return 8
   631			}
   632		default:
   633			ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
   634		}
   635		return 0
   636	}
   637	
   638	func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
   639		p := cursym.Func.Text
   640		if p == nil || p.Link == nil { // handle external functions and ELF section symbols
   641			return
   642		}
   643	
   644		if oprange[AANDN&obj.AMask] == nil {
   645			ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
   646		}
   647	
   648		c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
   649	
   650		pc := int64(0)
   651		p.Pc = pc
   652	
   653		var m int
   654		var o *Optab
   655		for p = p.Link; p != nil; p = p.Link {
   656			p.Pc = pc
   657			o = c.oplook(p)
   658			m = int(o.size)
   659			if m == 0 {
   660				if p.As == obj.APCALIGN {
   661					a := c.vregoff(&p.From)
   662					m = addpad(pc, a, ctxt)
   663				} else {
   664					if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   665						ctxt.Diag("zero-width instruction\n%v", p)
   666					}
   667					continue
   668				}
   669			}
   670			pc += int64(m)
   671		}
   672	
   673		c.cursym.Size = pc
   674	
   675		/*
   676		 * if any procedure is large enough to
   677		 * generate a large SBRA branch, then
   678		 * generate extra passes putting branches
   679		 * around jmps to fix. this is rare.
   680		 */
   681		bflag := 1
   682	
   683		var otxt int64
   684		var q *obj.Prog
   685		for bflag != 0 {
   686			bflag = 0
   687			pc = 0
   688			for p = c.cursym.Func.Text.Link; p != nil; p = p.Link {
   689				p.Pc = pc
   690				o = c.oplook(p)
   691	
   692				// very large conditional branches
   693				if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil {
   694					otxt = p.Pcond.Pc - pc
   695					if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
   696						q = c.newprog()
   697						q.Link = p.Link
   698						p.Link = q
   699						q.As = ABR
   700						q.To.Type = obj.TYPE_BRANCH
   701						q.Pcond = p.Pcond
   702						p.Pcond = q
   703						q = c.newprog()
   704						q.Link = p.Link
   705						p.Link = q
   706						q.As = ABR
   707						q.To.Type = obj.TYPE_BRANCH
   708						q.Pcond = q.Link.Link
   709	
   710						//addnop(p->link);
   711						//addnop(p);
   712						bflag = 1
   713					}
   714				}
   715	
   716				m = int(o.size)
   717				if m == 0 {
   718					if p.As == obj.APCALIGN {
   719						a := c.vregoff(&p.From)
   720						m = addpad(pc, a, ctxt)
   721					} else {
   722						if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
   723							ctxt.Diag("zero-width instruction\n%v", p)
   724						}
   725						continue
   726					}
   727				}
   728	
   729				pc += int64(m)
   730			}
   731	
   732			c.cursym.Size = pc
   733		}
   734	
   735		if pc%funcAlign != 0 {
   736			pc += funcAlign - (pc % funcAlign)
   737		}
   738	
   739		c.cursym.Size = pc
   740	
   741		/*
   742		 * lay out the code, emitting code and data relocations.
   743		 */
   744	
   745		c.cursym.Grow(c.cursym.Size)
   746	
   747		bp := c.cursym.P
   748		var i int32
   749		var out [6]uint32
   750		for p := c.cursym.Func.Text.Link; p != nil; p = p.Link {
   751			c.pc = p.Pc
   752			o = c.oplook(p)
   753			if int(o.size) > 4*len(out) {
   754				log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
   755			}
   756			origsize := o.size
   757			c.asmout(p, o, out[:])
   758			if origsize == 0 && o.size > 0 {
   759				for i = 0; i < int32(o.size/4); i++ {
   760					c.ctxt.Arch.ByteOrder.PutUint32(bp, out[0])
   761					bp = bp[4:]
   762				}
   763				o.size = origsize
   764			} else {
   765				for i = 0; i < int32(o.size/4); i++ {
   766					c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
   767					bp = bp[4:]
   768				}
   769			}
   770		}
   771	}
   772	
   773	func isint32(v int64) bool {
   774		return int64(int32(v)) == v
   775	}
   776	
   777	func isuint32(v uint64) bool {
   778		return uint64(uint32(v)) == v
   779	}
   780	
   781	func (c *ctxt9) aclass(a *obj.Addr) int {
   782		switch a.Type {
   783		case obj.TYPE_NONE:
   784			return C_NONE
   785	
   786		case obj.TYPE_REG:
   787			if REG_R0 <= a.Reg && a.Reg <= REG_R31 {
   788				return C_REG
   789			}
   790			if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
   791				return C_FREG
   792			}
   793			if REG_V0 <= a.Reg && a.Reg <= REG_V31 {
   794				return C_VREG
   795			}
   796			if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 {
   797				return C_VSREG
   798			}
   799			if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR {
   800				return C_CREG
   801			}
   802			if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 {
   803				switch a.Reg {
   804				case REG_LR:
   805					return C_LR
   806	
   807				case REG_XER:
   808					return C_XER
   809	
   810				case REG_CTR:
   811					return C_CTR
   812				}
   813	
   814				return C_SPR
   815			}
   816	
   817			if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 {
   818				return C_SPR
   819			}
   820			if a.Reg == REG_FPSCR {
   821				return C_FPSCR
   822			}
   823			if a.Reg == REG_MSR {
   824				return C_MSR
   825			}
   826			return C_GOK
   827	
   828		case obj.TYPE_MEM:
   829			switch a.Name {
   830			case obj.NAME_EXTERN,
   831				obj.NAME_STATIC:
   832				if a.Sym == nil {
   833					break
   834				}
   835				c.instoffset = a.Offset
   836				if a.Sym != nil { // use relocation
   837					if a.Sym.Type == objabi.STLSBSS {
   838						if c.ctxt.Flag_shared {
   839							return C_TLS_IE
   840						} else {
   841							return C_TLS_LE
   842						}
   843					}
   844					return C_ADDR
   845				}
   846				return C_LEXT
   847	
   848			case obj.NAME_GOTREF:
   849				return C_GOTADDR
   850	
   851			case obj.NAME_TOCREF:
   852				return C_TOCADDR
   853	
   854			case obj.NAME_AUTO:
   855				c.instoffset = int64(c.autosize) + a.Offset
   856				if c.instoffset >= -BIG && c.instoffset < BIG {
   857					return C_SAUTO
   858				}
   859				return C_LAUTO
   860	
   861			case obj.NAME_PARAM:
   862				c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
   863				if c.instoffset >= -BIG && c.instoffset < BIG {
   864					return C_SAUTO
   865				}
   866				return C_LAUTO
   867	
   868			case obj.NAME_NONE:
   869				c.instoffset = a.Offset
   870				if c.instoffset == 0 {
   871					return C_ZOREG
   872				}
   873				if c.instoffset >= -BIG && c.instoffset < BIG {
   874					return C_SOREG
   875				}
   876				return C_LOREG
   877			}
   878	
   879			return C_GOK
   880	
   881		case obj.TYPE_TEXTSIZE:
   882			return C_TEXTSIZE
   883	
   884		case obj.TYPE_FCONST:
   885			// The only cases where FCONST will occur are with float64 +/- 0.
   886			// All other float constants are generated in memory.
   887			f64 := a.Val.(float64)
   888			if f64 == 0 {
   889				if math.Signbit(f64) {
   890					return C_ADDCON
   891				}
   892				return C_ZCON
   893			}
   894			log.Fatalf("Unexpected nonzero FCONST operand %v", a)
   895	
   896		case obj.TYPE_CONST,
   897			obj.TYPE_ADDR:
   898			switch a.Name {
   899			case obj.NAME_NONE:
   900				c.instoffset = a.Offset
   901				if a.Reg != 0 {
   902					if -BIG <= c.instoffset && c.instoffset <= BIG {
   903						return C_SACON
   904					}
   905					if isint32(c.instoffset) {
   906						return C_LACON
   907					}
   908					return C_DACON
   909				}
   910	
   911			case obj.NAME_EXTERN,
   912				obj.NAME_STATIC:
   913				s := a.Sym
   914				if s == nil {
   915					return C_GOK
   916				}
   917	
   918				c.instoffset = a.Offset
   919	
   920				/* not sure why this barfs */
   921				return C_LCON
   922	
   923			case obj.NAME_AUTO:
   924				c.instoffset = int64(c.autosize) + a.Offset
   925				if c.instoffset >= -BIG && c.instoffset < BIG {
   926					return C_SACON
   927				}
   928				return C_LACON
   929	
   930			case obj.NAME_PARAM:
   931				c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize()
   932				if c.instoffset >= -BIG && c.instoffset < BIG {
   933					return C_SACON
   934				}
   935				return C_LACON
   936	
   937			default:
   938				return C_GOK
   939			}
   940	
   941			if c.instoffset >= 0 {
   942				if c.instoffset == 0 {
   943					return C_ZCON
   944				}
   945				if c.instoffset <= 0x7fff {
   946					return C_SCON
   947				}
   948				if c.instoffset <= 0xffff {
   949					return C_ANDCON
   950				}
   951				if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */
   952					return C_UCON
   953				}
   954				if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) {
   955					return C_LCON
   956				}
   957				return C_DCON
   958			}
   959	
   960			if c.instoffset >= -0x8000 {
   961				return C_ADDCON
   962			}
   963			if c.instoffset&0xffff == 0 && isint32(c.instoffset) {
   964				return C_UCON
   965			}
   966			if isint32(c.instoffset) {
   967				return C_LCON
   968			}
   969			return C_DCON
   970	
   971		case obj.TYPE_BRANCH:
   972			if a.Sym != nil && c.ctxt.Flag_dynlink {
   973				return C_LBRAPIC
   974			}
   975			return C_SBRA
   976		}
   977	
   978		return C_GOK
   979	}
   980	
   981	func prasm(p *obj.Prog) {
   982		fmt.Printf("%v\n", p)
   983	}
   984	
   985	func (c *ctxt9) oplook(p *obj.Prog) *Optab {
   986		a1 := int(p.Optab)
   987		if a1 != 0 {
   988			return &optab[a1-1]
   989		}
   990		a1 = int(p.From.Class)
   991		if a1 == 0 {
   992			a1 = c.aclass(&p.From) + 1
   993			p.From.Class = int8(a1)
   994		}
   995	
   996		a1--
   997		a3 := C_NONE + 1
   998		if p.GetFrom3() != nil {
   999			a3 = int(p.GetFrom3().Class)
  1000			if a3 == 0 {
  1001				a3 = c.aclass(p.GetFrom3()) + 1
  1002				p.GetFrom3().Class = int8(a3)
  1003			}
  1004		}
  1005	
  1006		a3--
  1007		a4 := int(p.To.Class)
  1008		if a4 == 0 {
  1009			a4 = c.aclass(&p.To) + 1
  1010			p.To.Class = int8(a4)
  1011		}
  1012	
  1013		a4--
  1014		a2 := C_NONE
  1015		if p.Reg != 0 {
  1016			if REG_R0 <= p.Reg && p.Reg <= REG_R31 {
  1017				a2 = C_REG
  1018			} else if REG_V0 <= p.Reg && p.Reg <= REG_V31 {
  1019				a2 = C_VREG
  1020			} else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 {
  1021				a2 = C_VSREG
  1022			} else if REG_F0 <= p.Reg && p.Reg <= REG_F31 {
  1023				a2 = C_FREG
  1024			}
  1025		}
  1026	
  1027		// c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4)
  1028		ops := oprange[p.As&obj.AMask]
  1029		c1 := &xcmp[a1]
  1030		c3 := &xcmp[a3]
  1031		c4 := &xcmp[a4]
  1032		for i := range ops {
  1033			op := &ops[i]
  1034			if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] {
  1035				p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
  1036				return op
  1037			}
  1038		}
  1039	
  1040		c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4))
  1041		prasm(p)
  1042		if ops == nil {
  1043			ops = optab
  1044		}
  1045		return &ops[0]
  1046	}
  1047	
  1048	func cmp(a int, b int) bool {
  1049		if a == b {
  1050			return true
  1051		}
  1052		switch a {
  1053		case C_LCON:
  1054			if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON {
  1055				return true
  1056			}
  1057	
  1058		case C_ADDCON:
  1059			if b == C_ZCON || b == C_SCON {
  1060				return true
  1061			}
  1062	
  1063		case C_ANDCON:
  1064			if b == C_ZCON || b == C_SCON {
  1065				return true
  1066			}
  1067	
  1068		case C_SPR:
  1069			if b == C_LR || b == C_XER || b == C_CTR {
  1070				return true
  1071			}
  1072	
  1073		case C_UCON:
  1074			if b == C_ZCON {
  1075				return true
  1076			}
  1077	
  1078		case C_SCON:
  1079			if b == C_ZCON {
  1080				return true
  1081			}
  1082	
  1083		case C_LACON:
  1084			if b == C_SACON {
  1085				return true
  1086			}
  1087	
  1088		case C_LBRA:
  1089			if b == C_SBRA {
  1090				return true
  1091			}
  1092	
  1093		case C_LEXT:
  1094			if b == C_SEXT {
  1095				return true
  1096			}
  1097	
  1098		case C_LAUTO:
  1099			if b == C_SAUTO {
  1100				return true
  1101			}
  1102	
  1103		case C_REG:
  1104			if b == C_ZCON {
  1105				return r0iszero != 0 /*TypeKind(100016)*/
  1106			}
  1107	
  1108		case C_LOREG:
  1109			if b == C_ZOREG || b == C_SOREG {
  1110				return true
  1111			}
  1112	
  1113		case C_SOREG:
  1114			if b == C_ZOREG {
  1115				return true
  1116			}
  1117	
  1118		case C_ANY:
  1119			return true
  1120		}
  1121	
  1122		return false
  1123	}
  1124	
  1125	type ocmp []Optab
  1126	
  1127	func (x ocmp) Len() int {
  1128		return len(x)
  1129	}
  1130	
  1131	func (x ocmp) Swap(i, j int) {
  1132		x[i], x[j] = x[j], x[i]
  1133	}
  1134	
  1135	// Used when sorting the optab. Sorting is
  1136	// done in a way so that the best choice of
  1137	// opcode/operand combination is considered first.
  1138	func (x ocmp) Less(i, j int) bool {
  1139		p1 := &x[i]
  1140		p2 := &x[j]
  1141		n := int(p1.as) - int(p2.as)
  1142		// same opcode
  1143		if n != 0 {
  1144			return n < 0
  1145		}
  1146		// Consider those that generate fewer
  1147		// instructions first.
  1148		n = int(p1.size) - int(p2.size)
  1149		if n != 0 {
  1150			return n < 0
  1151		}
  1152		// operand order should match
  1153		// better choices first
  1154		n = int(p1.a1) - int(p2.a1)
  1155		if n != 0 {
  1156			return n < 0
  1157		}
  1158		n = int(p1.a2) - int(p2.a2)
  1159		if n != 0 {
  1160			return n < 0
  1161		}
  1162		n = int(p1.a3) - int(p2.a3)
  1163		if n != 0 {
  1164			return n < 0
  1165		}
  1166		n = int(p1.a4) - int(p2.a4)
  1167		if n != 0 {
  1168			return n < 0
  1169		}
  1170		return false
  1171	}
  1172	
  1173	// Add an entry to the opcode table for
  1174	// a new opcode b0 with the same operand combinations
  1175	// as opcode a.
  1176	func opset(a, b0 obj.As) {
  1177		oprange[a&obj.AMask] = oprange[b0]
  1178	}
  1179	
  1180	// Build the opcode table
  1181	func buildop(ctxt *obj.Link) {
  1182		if oprange[AANDN&obj.AMask] != nil {
  1183			// Already initialized; stop now.
  1184			// This happens in the cmd/asm tests,
  1185			// each of which re-initializes the arch.
  1186			return
  1187		}
  1188	
  1189		var n int
  1190	
  1191		for i := 0; i < C_NCLASS; i++ {
  1192			for n = 0; n < C_NCLASS; n++ {
  1193				if cmp(n, i) {
  1194					xcmp[i][n] = true
  1195				}
  1196			}
  1197		}
  1198		for n = 0; optab[n].as != obj.AXXX; n++ {
  1199		}
  1200		sort.Sort(ocmp(optab[:n]))
  1201		for i := 0; i < n; i++ {
  1202			r := optab[i].as
  1203			r0 := r & obj.AMask
  1204			start := i
  1205			for optab[i].as == r {
  1206				i++
  1207			}
  1208			oprange[r0] = optab[start:i]
  1209			i--
  1210	
  1211			switch r {
  1212			default:
  1213				ctxt.Diag("unknown op in build: %v", r)
  1214				log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
  1215	
  1216			case ADCBF: /* unary indexed: op (b+a); op (b) */
  1217				opset(ADCBI, r0)
  1218	
  1219				opset(ADCBST, r0)
  1220				opset(ADCBT, r0)
  1221				opset(ADCBTST, r0)
  1222				opset(ADCBZ, r0)
  1223				opset(AICBI, r0)
  1224	
  1225			case AECOWX: /* indexed store: op s,(b+a); op s,(b) */
  1226				opset(ASTWCCC, r0)
  1227				opset(ASTBCCC, r0)
  1228	
  1229				opset(ASTDCCC, r0)
  1230	
  1231			case AREM: /* macro */
  1232				opset(AREMCC, r0)
  1233	
  1234				opset(AREMV, r0)
  1235				opset(AREMVCC, r0)
  1236	
  1237			case AREMU:
  1238				opset(AREMU, r0)
  1239				opset(AREMUCC, r0)
  1240				opset(AREMUV, r0)
  1241				opset(AREMUVCC, r0)
  1242	
  1243			case AREMD:
  1244				opset(AREMDCC, r0)
  1245				opset(AREMDV, r0)
  1246				opset(AREMDVCC, r0)
  1247	
  1248			case AREMDU:
  1249				opset(AREMDU, r0)
  1250				opset(AREMDUCC, r0)
  1251				opset(AREMDUV, r0)
  1252				opset(AREMDUVCC, r0)
  1253	
  1254			case ADIVW: /* op Rb[,Ra],Rd */
  1255				opset(AMULHW, r0)
  1256	
  1257				opset(AMULHWCC, r0)
  1258				opset(AMULHWU, r0)
  1259				opset(AMULHWUCC, r0)
  1260				opset(AMULLWCC, r0)
  1261				opset(AMULLWVCC, r0)
  1262				opset(AMULLWV, r0)
  1263				opset(ADIVWCC, r0)
  1264				opset(ADIVWV, r0)
  1265				opset(ADIVWVCC, r0)
  1266				opset(ADIVWU, r0)
  1267				opset(ADIVWUCC, r0)
  1268				opset(ADIVWUV, r0)
  1269				opset(ADIVWUVCC, r0)
  1270				opset(AADDCC, r0)
  1271				opset(AADDCV, r0)
  1272				opset(AADDCVCC, r0)
  1273				opset(AADDV, r0)
  1274				opset(AADDVCC, r0)
  1275				opset(AADDE, r0)
  1276				opset(AADDECC, r0)
  1277				opset(AADDEV, r0)
  1278				opset(AADDEVCC, r0)
  1279				opset(ACRAND, r0)
  1280				opset(ACRANDN, r0)
  1281				opset(ACREQV, r0)
  1282				opset(ACRNAND, r0)
  1283				opset(ACRNOR, r0)
  1284				opset(ACROR, r0)
  1285				opset(ACRORN, r0)
  1286				opset(ACRXOR, r0)
  1287				opset(AMULHD, r0)
  1288				opset(AMULHDCC, r0)
  1289				opset(AMULHDU, r0)
  1290				opset(AMULHDUCC, r0)
  1291				opset(AMULLD, r0)
  1292				opset(AMULLDCC, r0)
  1293				opset(AMULLDVCC, r0)
  1294				opset(AMULLDV, r0)
  1295				opset(ADIVD, r0)
  1296				opset(ADIVDCC, r0)
  1297				opset(ADIVDE, r0)
  1298				opset(ADIVDEU, r0)
  1299				opset(ADIVDECC, r0)
  1300				opset(ADIVDEUCC, r0)
  1301				opset(ADIVDVCC, r0)
  1302				opset(ADIVDV, r0)
  1303				opset(ADIVDU, r0)
  1304				opset(ADIVDUCC, r0)
  1305				opset(ADIVDUVCC, r0)
  1306				opset(ADIVDUCC, r0)
  1307	
  1308			case APOPCNTD: /* popcntd, popcntw, popcntb, cnttzw, cnttzd */
  1309				opset(APOPCNTW, r0)
  1310				opset(APOPCNTB, r0)
  1311				opset(ACNTTZW, r0)
  1312				opset(ACNTTZWCC, r0)
  1313				opset(ACNTTZD, r0)
  1314				opset(ACNTTZDCC, r0)
  1315	
  1316			case ACOPY: /* copy, paste. */
  1317				opset(APASTECC, r0)
  1318	
  1319			case AMADDHD: /* maddhd, maddhdu, maddld */
  1320				opset(AMADDHDU, r0)
  1321				opset(AMADDLD, r0)
  1322	
  1323			case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */
  1324				opset(AMOVH, r0)
  1325				opset(AMOVHZ, r0)
  1326	
  1327			case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */
  1328				opset(AMOVHU, r0)
  1329	
  1330				opset(AMOVHZU, r0)
  1331				opset(AMOVWU, r0)
  1332				opset(AMOVWZU, r0)
  1333				opset(AMOVDU, r0)
  1334				opset(AMOVMW, r0)
  1335	
  1336			case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */
  1337				opset(ALVEBX, r0)
  1338				opset(ALVEHX, r0)
  1339				opset(ALVEWX, r0)
  1340				opset(ALVX, r0)
  1341				opset(ALVXL, r0)
  1342				opset(ALVSL, r0)
  1343				opset(ALVSR, r0)
  1344	
  1345			case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */
  1346				opset(ASTVEBX, r0)
  1347				opset(ASTVEHX, r0)
  1348				opset(ASTVEWX, r0)
  1349				opset(ASTVX, r0)
  1350				opset(ASTVXL, r0)
  1351	
  1352			case AVAND: /* vand, vandc, vnand */
  1353				opset(AVAND, r0)
  1354				opset(AVANDC, r0)
  1355				opset(AVNAND, r0)
  1356	
  1357			case AVOR: /* vor, vorc, vxor, vnor, veqv */
  1358				opset(AVOR, r0)
  1359				opset(AVORC, r0)
  1360				opset(AVXOR, r0)
  1361				opset(AVNOR, r0)
  1362				opset(AVEQV, r0)
  1363	
  1364			case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */
  1365				opset(AVADDUBM, r0)
  1366				opset(AVADDUHM, r0)
  1367				opset(AVADDUWM, r0)
  1368				opset(AVADDUDM, r0)
  1369				opset(AVADDUQM, r0)
  1370	
  1371			case AVADDCU: /* vaddcuq, vaddcuw */
  1372				opset(AVADDCUQ, r0)
  1373				opset(AVADDCUW, r0)
  1374	
  1375			case AVADDUS: /* vaddubs, vadduhs, vadduws */
  1376				opset(AVADDUBS, r0)
  1377				opset(AVADDUHS, r0)
  1378				opset(AVADDUWS, r0)
  1379	
  1380			case AVADDSS: /* vaddsbs, vaddshs, vaddsws */
  1381				opset(AVADDSBS, r0)
  1382				opset(AVADDSHS, r0)
  1383				opset(AVADDSWS, r0)
  1384	
  1385			case AVADDE: /* vaddeuqm, vaddecuq */
  1386				opset(AVADDEUQM, r0)
  1387				opset(AVADDECUQ, r0)
  1388	
  1389			case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */
  1390				opset(AVSUBUBM, r0)
  1391				opset(AVSUBUHM, r0)
  1392				opset(AVSUBUWM, r0)
  1393				opset(AVSUBUDM, r0)
  1394				opset(AVSUBUQM, r0)
  1395	
  1396			case AVSUBCU: /* vsubcuq, vsubcuw */
  1397				opset(AVSUBCUQ, r0)
  1398				opset(AVSUBCUW, r0)
  1399	
  1400			case AVSUBUS: /* vsububs, vsubuhs, vsubuws */
  1401				opset(AVSUBUBS, r0)
  1402				opset(AVSUBUHS, r0)
  1403				opset(AVSUBUWS, r0)
  1404	
  1405			case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */
  1406				opset(AVSUBSBS, r0)
  1407				opset(AVSUBSHS, r0)
  1408				opset(AVSUBSWS, r0)
  1409	
  1410			case AVSUBE: /* vsubeuqm, vsubecuq */
  1411				opset(AVSUBEUQM, r0)
  1412				opset(AVSUBECUQ, r0)
  1413	
  1414			case AVMULESB: /* vmulesb, vmulosb, vmuleub, vmuloub, vmulosh, vmulouh, vmulesw, vmulosw, vmuleuw, vmulouw, vmuluwm */
  1415				opset(AVMULOSB, r0)
  1416				opset(AVMULEUB, r0)
  1417				opset(AVMULOUB, r0)
  1418				opset(AVMULESH, r0)
  1419				opset(AVMULOSH, r0)
  1420				opset(AVMULEUH, r0)
  1421				opset(AVMULOUH, r0)
  1422				opset(AVMULESW, r0)
  1423				opset(AVMULOSW, r0)
  1424				opset(AVMULEUW, r0)
  1425				opset(AVMULOUW, r0)
  1426				opset(AVMULUWM, r0)
  1427			case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */
  1428				opset(AVPMSUMB, r0)
  1429				opset(AVPMSUMH, r0)
  1430				opset(AVPMSUMW, r0)
  1431				opset(AVPMSUMD, r0)
  1432	
  1433			case AVR: /* vrlb, vrlh, vrlw, vrld */
  1434				opset(AVRLB, r0)
  1435				opset(AVRLH, r0)
  1436				opset(AVRLW, r0)
  1437				opset(AVRLD, r0)
  1438	
  1439			case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */
  1440				opset(AVSLB, r0)
  1441				opset(AVSLH, r0)
  1442				opset(AVSLW, r0)
  1443				opset(AVSL, r0)
  1444				opset(AVSLO, r0)
  1445				opset(AVSRB, r0)
  1446				opset(AVSRH, r0)
  1447				opset(AVSRW, r0)
  1448				opset(AVSR, r0)
  1449				opset(AVSRO, r0)
  1450				opset(AVSLD, r0)
  1451				opset(AVSRD, r0)
  1452	
  1453			case AVSA: /* vsrab, vsrah, vsraw, vsrad */
  1454				opset(AVSRAB, r0)
  1455				opset(AVSRAH, r0)
  1456				opset(AVSRAW, r0)
  1457				opset(AVSRAD, r0)
  1458	
  1459			case AVSOI: /* vsldoi */
  1460				opset(AVSLDOI, r0)
  1461	
  1462			case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
  1463				opset(AVCLZB, r0)
  1464				opset(AVCLZH, r0)
  1465				opset(AVCLZW, r0)
  1466				opset(AVCLZD, r0)
  1467	
  1468			case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */
  1469				opset(AVPOPCNTB, r0)
  1470				opset(AVPOPCNTH, r0)
  1471				opset(AVPOPCNTW, r0)
  1472				opset(AVPOPCNTD, r0)
  1473	
  1474			case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */
  1475				opset(AVCMPEQUB, r0)
  1476				opset(AVCMPEQUBCC, r0)
  1477				opset(AVCMPEQUH, r0)
  1478				opset(AVCMPEQUHCC, r0)
  1479				opset(AVCMPEQUW, r0)
  1480				opset(AVCMPEQUWCC, r0)
  1481				opset(AVCMPEQUD, r0)
  1482				opset(AVCMPEQUDCC, r0)
  1483	
  1484			case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */
  1485				opset(AVCMPGTUB, r0)
  1486				opset(AVCMPGTUBCC, r0)
  1487				opset(AVCMPGTUH, r0)
  1488				opset(AVCMPGTUHCC, r0)
  1489				opset(AVCMPGTUW, r0)
  1490				opset(AVCMPGTUWCC, r0)
  1491				opset(AVCMPGTUD, r0)
  1492				opset(AVCMPGTUDCC, r0)
  1493				opset(AVCMPGTSB, r0)
  1494				opset(AVCMPGTSBCC, r0)
  1495				opset(AVCMPGTSH, r0)
  1496				opset(AVCMPGTSHCC, r0)
  1497				opset(AVCMPGTSW, r0)
  1498				opset(AVCMPGTSWCC, r0)
  1499				opset(AVCMPGTSD, r0)
  1500				opset(AVCMPGTSDCC, r0)
  1501	
  1502			case AVCMPNEZB: /* vcmpnezb[.] */
  1503				opset(AVCMPNEZBCC, r0)
  1504	
  1505			case AVPERM: /* vperm */
  1506				opset(AVPERMXOR, r0)
  1507	
  1508			case AVBPERMQ: /* vbpermq, vbpermd */
  1509				opset(AVBPERMD, r0)
  1510	
  1511			case AVSEL: /* vsel */
  1512				opset(AVSEL, r0)
  1513	
  1514			case AVSPLT: /* vspltb, vsplth, vspltw */
  1515				opset(AVSPLTB, r0)
  1516				opset(AVSPLTH, r0)
  1517				opset(AVSPLTW, r0)
  1518	
  1519			case AVSPLTI: /* vspltisb, vspltish, vspltisw */
  1520				opset(AVSPLTISB, r0)
  1521				opset(AVSPLTISH, r0)
  1522				opset(AVSPLTISW, r0)
  1523	
  1524			case AVCIPH: /* vcipher, vcipherlast */
  1525				opset(AVCIPHER, r0)
  1526				opset(AVCIPHERLAST, r0)
  1527	
  1528			case AVNCIPH: /* vncipher, vncipherlast */
  1529				opset(AVNCIPHER, r0)
  1530				opset(AVNCIPHERLAST, r0)
  1531	
  1532			case AVSBOX: /* vsbox */
  1533				opset(AVSBOX, r0)
  1534	
  1535			case AVSHASIGMA: /* vshasigmaw, vshasigmad */
  1536				opset(AVSHASIGMAW, r0)
  1537				opset(AVSHASIGMAD, r0)
  1538	
  1539			case ALXV: /* lxvd2x, lxvdsx, lxvw4x */
  1540				opset(ALXVD2X, r0)
  1541				opset(ALXVDSX, r0)
  1542				opset(ALXVW4X, r0)
  1543	
  1544			case ASTXV: /* stxvd2x, stxvdsx, stxvw4x */
  1545				opset(ASTXVD2X, r0)
  1546				opset(ASTXVW4X, r0)
  1547	
  1548			case ALXS: /* lxsdx  */
  1549				opset(ALXSDX, r0)
  1550	
  1551			case ASTXS: /* stxsdx */
  1552				opset(ASTXSDX, r0)
  1553	
  1554			case ALXSI: /* lxsiwax, lxsiwzx  */
  1555				opset(ALXSIWAX, r0)
  1556				opset(ALXSIWZX, r0)
  1557	
  1558			case ASTXSI: /* stxsiwx */
  1559				opset(ASTXSIWX, r0)
  1560	
  1561			case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */
  1562				opset(AMFVSRD, r0)
  1563				opset(AMFFPRD, r0)
  1564				opset(AMFVRD, r0)
  1565				opset(AMFVSRWZ, r0)
  1566				opset(AMFVSRLD, r0)
  1567	
  1568			case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */
  1569				opset(AMTVSRD, r0)
  1570				opset(AMTFPRD, r0)
  1571				opset(AMTVRD, r0)
  1572				opset(AMTVSRWA, r0)
  1573				opset(AMTVSRWZ, r0)
  1574				opset(AMTVSRDD, r0)
  1575				opset(AMTVSRWS, r0)
  1576	
  1577			case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */
  1578				opset(AXXLANDQ, r0)
  1579				opset(AXXLANDC, r0)
  1580				opset(AXXLEQV, r0)
  1581				opset(AXXLNAND, r0)
  1582	
  1583			case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */
  1584				opset(AXXLORC, r0)
  1585				opset(AXXLNOR, r0)
  1586				opset(AXXLORQ, r0)
  1587				opset(AXXLXOR, r0)
  1588	
  1589			case AXXSEL: /* xxsel */
  1590				opset(AXXSEL, r0)
  1591	
  1592			case AXXMRG: /* xxmrghw, xxmrglw */
  1593				opset(AXXMRGHW, r0)
  1594				opset(AXXMRGLW, r0)
  1595	
  1596			case AXXSPLT: /* xxspltw */
  1597				opset(AXXSPLTW, r0)
  1598	
  1599			case AXXPERM: /* xxpermdi */
  1600				opset(AXXPERMDI, r0)
  1601	
  1602			case AXXSI: /* xxsldwi */
  1603				opset(AXXSLDWI, r0)
  1604	
  1605			case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */
  1606				opset(AXSCVDPSP, r0)
  1607				opset(AXSCVSPDP, r0)
  1608				opset(AXSCVDPSPN, r0)
  1609				opset(AXSCVSPDPN, r0)
  1610	
  1611			case AXVCV: /* xvcvdpsp, xvcvspdp */
  1612				opset(AXVCVDPSP, r0)
  1613				opset(AXVCVSPDP, r0)
  1614	
  1615			case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */
  1616				opset(AXSCVDPSXDS, r0)
  1617				opset(AXSCVDPSXWS, r0)
  1618				opset(AXSCVDPUXDS, r0)
  1619				opset(AXSCVDPUXWS, r0)
  1620	
  1621			case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */
  1622				opset(AXSCVSXDDP, r0)
  1623				opset(AXSCVUXDDP, r0)
  1624				opset(AXSCVSXDSP, r0)
  1625				opset(AXSCVUXDSP, r0)
  1626	
  1627			case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */
  1628				opset(AXVCVDPSXDS, r0)
  1629				opset(AXVCVDPSXWS, r0)
  1630				opset(AXVCVDPUXDS, r0)
  1631				opset(AXVCVDPUXWS, r0)
  1632				opset(AXVCVSPSXDS, r0)
  1633				opset(AXVCVSPSXWS, r0)
  1634				opset(AXVCVSPUXDS, r0)
  1635				opset(AXVCVSPUXWS, r0)
  1636	
  1637			case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */
  1638				opset(AXVCVSXDDP, r0)
  1639				opset(AXVCVSXWDP, r0)
  1640				opset(AXVCVUXDDP, r0)
  1641				opset(AXVCVUXWDP, r0)
  1642				opset(AXVCVSXDSP, r0)
  1643				opset(AXVCVSXWSP, r0)
  1644				opset(AXVCVUXDSP, r0)
  1645				opset(AXVCVUXWSP, r0)
  1646	
  1647			case AAND: /* logical op Rb,Rs,Ra; no literal */
  1648				opset(AANDN, r0)
  1649				opset(AANDNCC, r0)
  1650				opset(AEQV, r0)
  1651				opset(AEQVCC, r0)
  1652				opset(ANAND, r0)
  1653				opset(ANANDCC, r0)
  1654				opset(ANOR, r0)
  1655				opset(ANORCC, r0)
  1656				opset(AORCC, r0)
  1657				opset(AORN, r0)
  1658				opset(AORNCC, r0)
  1659				opset(AXORCC, r0)
  1660	
  1661			case AADDME: /* op Ra, Rd */
  1662				opset(AADDMECC, r0)
  1663	
  1664				opset(AADDMEV, r0)
  1665				opset(AADDMEVCC, r0)
  1666				opset(AADDZE, r0)
  1667				opset(AADDZECC, r0)
  1668				opset(AADDZEV, r0)
  1669				opset(AADDZEVCC, r0)
  1670				opset(ASUBME, r0)
  1671				opset(ASUBMECC, r0)
  1672				opset(ASUBMEV, r0)
  1673				opset(ASUBMEVCC, r0)
  1674				opset(ASUBZE, r0)
  1675				opset(ASUBZECC, r0)
  1676				opset(ASUBZEV, r0)
  1677				opset(ASUBZEVCC, r0)
  1678	
  1679			case AADDC:
  1680				opset(AADDCCC, r0)
  1681	
  1682			case ABEQ:
  1683				opset(ABGE, r0)
  1684				opset(ABGT, r0)
  1685				opset(ABLE, r0)
  1686				opset(ABLT, r0)
  1687				opset(ABNE, r0)
  1688				opset(ABVC, r0)
  1689				opset(ABVS, r0)
  1690	
  1691			case ABR:
  1692				opset(ABL, r0)
  1693	
  1694			case ABC:
  1695				opset(ABCL, r0)
  1696	
  1697			case AEXTSB: /* op Rs, Ra */
  1698				opset(AEXTSBCC, r0)
  1699	
  1700				opset(AEXTSH, r0)
  1701				opset(AEXTSHCC, r0)
  1702				opset(ACNTLZW, r0)
  1703				opset(ACNTLZWCC, r0)
  1704				opset(ACNTLZD, r0)
  1705				opset(AEXTSW, r0)
  1706				opset(AEXTSWCC, r0)
  1707				opset(ACNTLZDCC, r0)
  1708	
  1709			case AFABS: /* fop [s,]d */
  1710				opset(AFABSCC, r0)
  1711	
  1712				opset(AFNABS, r0)
  1713				opset(AFNABSCC, r0)
  1714				opset(AFNEG, r0)
  1715				opset(AFNEGCC, r0)
  1716				opset(AFRSP, r0)
  1717				opset(AFRSPCC, r0)
  1718				opset(AFCTIW, r0)
  1719				opset(AFCTIWCC, r0)
  1720				opset(AFCTIWZ, r0)
  1721				opset(AFCTIWZCC, r0)
  1722				opset(AFCTID, r0)
  1723				opset(AFCTIDCC, r0)
  1724				opset(AFCTIDZ, r0)
  1725				opset(AFCTIDZCC, r0)
  1726				opset(AFCFID, r0)
  1727				opset(AFCFIDCC, r0)
  1728				opset(AFCFIDU, r0)
  1729				opset(AFCFIDUCC, r0)
  1730				opset(AFCFIDS, r0)
  1731				opset(AFCFIDSCC, r0)
  1732				opset(AFRES, r0)
  1733				opset(AFRESCC, r0)
  1734				opset(AFRIM, r0)
  1735				opset(AFRIMCC, r0)
  1736				opset(AFRIP, r0)
  1737				opset(AFRIPCC, r0)
  1738				opset(AFRIZ, r0)
  1739				opset(AFRIZCC, r0)
  1740				opset(AFRIN, r0)
  1741				opset(AFRINCC, r0)
  1742				opset(AFRSQRTE, r0)
  1743				opset(AFRSQRTECC, r0)
  1744				opset(AFSQRT, r0)
  1745				opset(AFSQRTCC, r0)
  1746				opset(AFSQRTS, r0)
  1747				opset(AFSQRTSCC, r0)
  1748	
  1749			case AFADD:
  1750				opset(AFADDS, r0)
  1751				opset(AFADDCC, r0)
  1752				opset(AFADDSCC, r0)
  1753				opset(AFCPSGN, r0)
  1754				opset(AFCPSGNCC, r0)
  1755				opset(AFDIV, r0)
  1756				opset(AFDIVS, r0)
  1757				opset(AFDIVCC, r0)
  1758				opset(AFDIVSCC, r0)
  1759				opset(AFSUB, r0)
  1760				opset(AFSUBS, r0)
  1761				opset(AFSUBCC, r0)
  1762				opset(AFSUBSCC, r0)
  1763	
  1764			case AFMADD:
  1765				opset(AFMADDCC, r0)
  1766				opset(AFMADDS, r0)
  1767				opset(AFMADDSCC, r0)
  1768				opset(AFMSUB, r0)
  1769				opset(AFMSUBCC, r0)
  1770				opset(AFMSUBS, r0)
  1771				opset(AFMSUBSCC, r0)
  1772				opset(AFNMADD, r0)
  1773				opset(AFNMADDCC, r0)
  1774				opset(AFNMADDS, r0)
  1775				opset(AFNMADDSCC, r0)
  1776				opset(AFNMSUB, r0)
  1777				opset(AFNMSUBCC, r0)
  1778				opset(AFNMSUBS, r0)
  1779				opset(AFNMSUBSCC, r0)
  1780				opset(AFSEL, r0)
  1781				opset(AFSELCC, r0)
  1782	
  1783			case AFMUL:
  1784				opset(AFMULS, r0)
  1785				opset(AFMULCC, r0)
  1786				opset(AFMULSCC, r0)
  1787	
  1788			case AFCMPO:
  1789				opset(AFCMPU, r0)
  1790	
  1791			case AISEL:
  1792				opset(AISEL, r0)
  1793	
  1794			case AMTFSB0:
  1795				opset(AMTFSB0CC, r0)
  1796				opset(AMTFSB1, r0)
  1797				opset(AMTFSB1CC, r0)
  1798	
  1799			case ANEG: /* op [Ra,] Rd */
  1800				opset(ANEGCC, r0)
  1801	
  1802				opset(ANEGV, r0)
  1803				opset(ANEGVCC, r0)
  1804	
  1805			case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,R */
  1806				opset(AXOR, r0)
  1807	
  1808			case AORIS: /* oris/xoris $uimm,Rs,Ra */
  1809				opset(AXORIS, r0)
  1810	
  1811			case ASLW:
  1812				opset(ASLWCC, r0)
  1813				opset(ASRW, r0)
  1814				opset(ASRWCC, r0)
  1815				opset(AROTLW, r0)
  1816	
  1817			case ASLD:
  1818				opset(ASLDCC, r0)
  1819				opset(ASRD, r0)
  1820				opset(ASRDCC, r0)
  1821				opset(AROTL, r0)
  1822	
  1823			case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1824				opset(ASRAWCC, r0)
  1825	
  1826			case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */
  1827				opset(ASRADCC, r0)
  1828	
  1829			case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */
  1830				opset(ASUB, r0)
  1831	
  1832				opset(ASUBCC, r0)
  1833				opset(ASUBV, r0)
  1834				opset(ASUBVCC, r0)
  1835				opset(ASUBCCC, r0)
  1836				opset(ASUBCV, r0)
  1837				opset(ASUBCVCC, r0)
  1838				opset(ASUBE, r0)
  1839				opset(ASUBECC, r0)
  1840				opset(ASUBEV, r0)
  1841				opset(ASUBEVCC, r0)
  1842	
  1843			case ASYNC:
  1844				opset(AISYNC, r0)
  1845				opset(ALWSYNC, r0)
  1846				opset(APTESYNC, r0)
  1847				opset(ATLBSYNC, r0)
  1848	
  1849			case ARLWMI:
  1850				opset(ARLWMICC, r0)
  1851				opset(ARLWNM, r0)
  1852				opset(ARLWNMCC, r0)
  1853	
  1854			case ARLDMI:
  1855				opset(ARLDMICC, r0)
  1856				opset(ARLDIMI, r0)
  1857				opset(ARLDIMICC, r0)
  1858	
  1859			case ARLDC:
  1860				opset(ARLDCCC, r0)
  1861	
  1862			case ARLDCL:
  1863				opset(ARLDCR, r0)
  1864				opset(ARLDCLCC, r0)
  1865				opset(ARLDCRCC, r0)
  1866	
  1867			case ARLDICL:
  1868				opset(ARLDICLCC, r0)
  1869				opset(ARLDICR, r0)
  1870				opset(ARLDICRCC, r0)
  1871	
  1872			case AFMOVD:
  1873				opset(AFMOVDCC, r0)
  1874				opset(AFMOVDU, r0)
  1875				opset(AFMOVS, r0)
  1876				opset(AFMOVSU, r0)
  1877	
  1878			case ALDAR:
  1879				opset(ALBAR, r0)
  1880				opset(ALHAR, r0)
  1881				opset(ALWAR, r0)
  1882	
  1883			case ASYSCALL: /* just the op; flow of control */
  1884				opset(ARFI, r0)
  1885	
  1886				opset(ARFCI, r0)
  1887				opset(ARFID, r0)
  1888				opset(AHRFID, r0)
  1889	
  1890			case AMOVHBR:
  1891				opset(AMOVWBR, r0)
  1892				opset(AMOVDBR, r0)
  1893	
  1894			case ASLBMFEE:
  1895				opset(ASLBMFEV, r0)
  1896	
  1897			case ATW:
  1898				opset(ATD, r0)
  1899	
  1900			case ATLBIE:
  1901				opset(ASLBIE, r0)
  1902				opset(ATLBIEL, r0)
  1903	
  1904			case AEIEIO:
  1905				opset(ASLBIA, r0)
  1906	
  1907			case ACMP:
  1908				opset(ACMPW, r0)
  1909	
  1910			case ACMPU:
  1911				opset(ACMPWU, r0)
  1912	
  1913			case ACMPB:
  1914				opset(ACMPB, r0)
  1915	
  1916			case AFTDIV:
  1917				opset(AFTDIV, r0)
  1918	
  1919			case AFTSQRT:
  1920				opset(AFTSQRT, r0)
  1921	
  1922			case AADD,
  1923				AADDIS,
  1924				AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */
  1925				AANDISCC,
  1926				AFMOVSX,
  1927				AFMOVSZ,
  1928				ALSW,
  1929				AMOVW,
  1930				/* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */
  1931				AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals  */
  1932				AMOVD,  /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */
  1933				AMOVB,  /* macro: move byte with sign extension */
  1934				AMOVBU, /* macro: move byte with sign extension & update */
  1935				AMOVFL,
  1936				AMULLW,
  1937				/* op $s[,r2],r3; op r1[,r2],r3; no cc/v */
  1938				ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */
  1939				ASTSW,
  1940				ASLBMTE,
  1941				AWORD,
  1942				ADWORD,
  1943				ADARN,
  1944				ALDMX,
  1945				AVMSUMUDM,
  1946				AADDEX,
  1947				ACMPEQB,
  1948				AECIWX,
  1949				obj.ANOP,
  1950				obj.ATEXT,
  1951				obj.AUNDEF,
  1952				obj.AFUNCDATA,
  1953				obj.APCALIGN,
  1954				obj.APCDATA,
  1955				obj.ADUFFZERO,
  1956				obj.ADUFFCOPY:
  1957				break
  1958			}
  1959		}
  1960	}
  1961	
  1962	func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
  1963		return o<<26 | xo<<1 | oe<<11
  1964	}
  1965	
  1966	func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
  1967		return o<<26 | xo<<2 | oe<<11
  1968	}
  1969	
  1970	func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
  1971		return o<<26 | xo<<3 | oe<<11
  1972	}
  1973	
  1974	func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
  1975		return o<<26 | xo<<4 | oe<<11
  1976	}
  1977	
  1978	func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  1979		return o<<26 | xo | oe<<11 | rc&1
  1980	}
  1981	
  1982	func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  1983		return o<<26 | xo | oe<<11 | (rc&1)<<10
  1984	}
  1985	
  1986	func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
  1987		return o<<26 | xo<<1 | oe<<10 | rc&1
  1988	}
  1989	
  1990	func OPCC(o uint32, xo uint32, rc uint32) uint32 {
  1991		return OPVCC(o, xo, 0, rc)
  1992	}
  1993	
  1994	func OP(o uint32, xo uint32) uint32 {
  1995		return OPVCC(o, xo, 0, 0)
  1996	}
  1997	
  1998	/* the order is dest, a/s, b/imm for both arithmetic and logical operations */
  1999	func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
  2000		return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
  2001	}
  2002	
  2003	/* VX-form 2-register operands, r/none/r */
  2004	func AOP_RR(op uint32, d uint32, a uint32) uint32 {
  2005		return op | (d&31)<<21 | (a&31)<<11
  2006	}
  2007	
  2008	/* VA-form 4-register operands */
  2009	func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2010		return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
  2011	}
  2012	
  2013	func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2014		return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
  2015	}
  2016	
  2017	/* VX-form 2-register + UIM operands */
  2018	func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
  2019		return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
  2020	}
  2021	
  2022	/* VX-form 2-register + ST + SIX operands */
  2023	func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
  2024		return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
  2025	}
  2026	
  2027	/* VA-form 3-register + SHB operands */
  2028	func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
  2029		return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
  2030	}
  2031	
  2032	/* VX-form 1-register + SIM operands */
  2033	func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
  2034		return op | (d&31)<<21 | (simm&31)<<16
  2035	}
  2036	
  2037	/* XX1-form 3-register operands, 1 VSR operand */
  2038	func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 {
  2039		/* For the XX-form encodings, we need the VSX register number to be exactly */
  2040		/* between 0-63, so we can properly set the rightmost bits. */
  2041		r := d - REG_VS0
  2042		return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
  2043	}
  2044	
  2045	/* XX2-form 3-register operands, 2 VSR operands */
  2046	func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 {
  2047		xt := d - REG_VS0
  2048		xb := b - REG_VS0
  2049		return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
  2050	}
  2051	
  2052	/* XX3-form 3 VSR operands */
  2053	func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 {
  2054		xt := d - REG_VS0
  2055		xa := a - REG_VS0
  2056		xb := b - REG_VS0
  2057		return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2058	}
  2059	
  2060	/* XX3-form 3 VSR operands + immediate */
  2061	func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2062		xt := d - REG_VS0
  2063		xa := a - REG_VS0
  2064		xb := b - REG_VS0
  2065		return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2066	}
  2067	
  2068	/* XX4-form, 4 VSR operands */
  2069	func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2070		xt := d - REG_VS0
  2071		xa := a - REG_VS0
  2072		xb := b - REG_VS0
  2073		xc := c - REG_VS0
  2074		return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
  2075	}
  2076	
  2077	/* Z23-form, 3-register operands + CY field */
  2078	func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2079		return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7
  2080	}
  2081	
  2082	/* X-form, 3-register operands + EH field */
  2083	func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
  2084		return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
  2085	}
  2086	
  2087	func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
  2088		return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
  2089	}
  2090	
  2091	func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
  2092		return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
  2093	}
  2094	
  2095	func OP_BR(op uint32, li uint32, aa uint32) uint32 {
  2096		return op | li&0x03FFFFFC | aa<<1
  2097	}
  2098	
  2099	func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
  2100		return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
  2101	}
  2102	
  2103	func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
  2104		return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
  2105	}
  2106	
  2107	func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
  2108		return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
  2109	}
  2110	
  2111	func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
  2112		return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
  2113	}
  2114	
  2115	func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
  2116		return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
  2117	}
  2118	
  2119	const (
  2120		/* each rhs is OPVCC(_, _, _, _) */
  2121		OP_ADD    = 31<<26 | 266<<1 | 0<<10 | 0
  2122		OP_ADDI   = 14<<26 | 0<<1 | 0<<10 | 0
  2123		OP_ADDIS  = 15<<26 | 0<<1 | 0<<10 | 0
  2124		OP_ANDI   = 28<<26 | 0<<1 | 0<<10 | 0
  2125		OP_EXTSB  = 31<<26 | 954<<1 | 0<<10 | 0
  2126		OP_EXTSH  = 31<<26 | 922<<1 | 0<<10 | 0
  2127		OP_EXTSW  = 31<<26 | 986<<1 | 0<<10 | 0
  2128		OP_ISEL   = 31<<26 | 15<<1 | 0<<10 | 0
  2129		OP_MCRF   = 19<<26 | 0<<1 | 0<<10 | 0
  2130		OP_MCRFS  = 63<<26 | 64<<1 | 0<<10 | 0
  2131		OP_MCRXR  = 31<<26 | 512<<1 | 0<<10 | 0
  2132		OP_MFCR   = 31<<26 | 19<<1 | 0<<10 | 0
  2133		OP_MFFS   = 63<<26 | 583<<1 | 0<<10 | 0
  2134		OP_MFMSR  = 31<<26 | 83<<1 | 0<<10 | 0
  2135		OP_MFSPR  = 31<<26 | 339<<1 | 0<<10 | 0
  2136		OP_MFSR   = 31<<26 | 595<<1 | 0<<10 | 0
  2137		OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
  2138		OP_MTCRF  = 31<<26 | 144<<1 | 0<<10 | 0
  2139		OP_MTFSF  = 63<<26 | 711<<1 | 0<<10 | 0
  2140		OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
  2141		OP_MTMSR  = 31<<26 | 146<<1 | 0<<10 | 0
  2142		OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0
  2143		OP_MTSPR  = 31<<26 | 467<<1 | 0<<10 | 0
  2144		OP_MTSR   = 31<<26 | 210<<1 | 0<<10 | 0
  2145		OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
  2146		OP_MULLW  = 31<<26 | 235<<1 | 0<<10 | 0
  2147		OP_MULLD  = 31<<26 | 233<<1 | 0<<10 | 0
  2148		OP_OR     = 31<<26 | 444<<1 | 0<<10 | 0
  2149		OP_ORI    = 24<<26 | 0<<1 | 0<<10 | 0
  2150		OP_ORIS   = 25<<26 | 0<<1 | 0<<10 | 0
  2151		OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
  2152		OP_RLWNM  = 23<<26 | 0<<1 | 0<<10 | 0
  2153		OP_SUBF   = 31<<26 | 40<<1 | 0<<10 | 0
  2154		OP_RLDIC  = 30<<26 | 4<<1 | 0<<10 | 0
  2155		OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
  2156		OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
  2157		OP_RLDCL  = 30<<26 | 8<<1 | 0<<10 | 0
  2158	)
  2159	
  2160	func oclass(a *obj.Addr) int {
  2161		return int(a.Class) - 1
  2162	}
  2163	
  2164	const (
  2165		D_FORM = iota
  2166		DS_FORM
  2167	)
  2168	
  2169	// This function determines when a non-indexed load or store is D or
  2170	// DS form for use in finding the size of the offset field in the instruction.
  2171	// The size is needed when setting the offset value in the instruction
  2172	// and when generating relocation for that field.
  2173	// DS form instructions include: ld, ldu, lwa, std, stdu.  All other
  2174	// loads and stores with an offset field are D form.  This function should
  2175	// only be called with the same opcodes as are handled by opstore and opload.
  2176	func (c *ctxt9) opform(insn uint32) int {
  2177		switch insn {
  2178		default:
  2179			c.ctxt.Diag("bad insn in loadform: %x", insn)
  2180		case OPVCC(58, 0, 0, 0), // ld
  2181			OPVCC(58, 0, 0, 1),        // ldu
  2182			OPVCC(58, 0, 0, 0) | 1<<1, // lwa
  2183			OPVCC(62, 0, 0, 0),        // std
  2184			OPVCC(62, 0, 0, 1):        //stdu
  2185			return DS_FORM
  2186		case OP_ADDI, // add
  2187			OPVCC(32, 0, 0, 0), // lwz
  2188			OPVCC(33, 0, 0, 0), // lwzu
  2189			OPVCC(34, 0, 0, 0), // lbz
  2190			OPVCC(35, 0, 0, 0), // lbzu
  2191			OPVCC(40, 0, 0, 0), // lhz
  2192			OPVCC(41, 0, 0, 0), // lhzu
  2193			OPVCC(42, 0, 0, 0), // lha
  2194			OPVCC(43, 0, 0, 0), // lhau
  2195			OPVCC(46, 0, 0, 0), // lmw
  2196			OPVCC(48, 0, 0, 0), // lfs
  2197			OPVCC(49, 0, 0, 0), // lfsu
  2198			OPVCC(50, 0, 0, 0), // lfd
  2199			OPVCC(51, 0, 0, 0), // lfdu
  2200			OPVCC(36, 0, 0, 0), // stw
  2201			OPVCC(37, 0, 0, 0), // stwu
  2202			OPVCC(38, 0, 0, 0), // stb
  2203			OPVCC(39, 0, 0, 0), // stbu
  2204			OPVCC(44, 0, 0, 0), // sth
  2205			OPVCC(45, 0, 0, 0), // sthu
  2206			OPVCC(47, 0, 0, 0), // stmw
  2207			OPVCC(52, 0, 0, 0), // stfs
  2208			OPVCC(53, 0, 0, 0), // stfsu
  2209			OPVCC(54, 0, 0, 0), // stfd
  2210			OPVCC(55, 0, 0, 0): // stfdu
  2211			return D_FORM
  2212		}
  2213		return 0
  2214	}
  2215	
  2216	// Encode instructions and create relocation for accessing s+d according to the
  2217	// instruction op with source or destination (as appropriate) register reg.
  2218	func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) {
  2219		if c.ctxt.Headtype == objabi.Haix {
  2220			// Every symbol access must be made via a TOC anchor.
  2221			c.ctxt.Diag("symbolAccess called for %s", s.Name)
  2222		}
  2223		var base uint32
  2224		form := c.opform(op)
  2225		if c.ctxt.Flag_shared {
  2226			base = REG_R2
  2227		} else {
  2228			base = REG_R0
  2229		}
  2230		o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
  2231		o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
  2232		rel := obj.Addrel(c.cursym)
  2233		rel.Off = int32(c.pc)
  2234		rel.Siz = 8
  2235		rel.Sym = s
  2236		rel.Add = d
  2237		if c.ctxt.Flag_shared {
  2238			switch form {
  2239			case D_FORM:
  2240				rel.Type = objabi.R_ADDRPOWER_TOCREL
  2241			case DS_FORM:
  2242				rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
  2243			}
  2244	
  2245		} else {
  2246			switch form {
  2247			case D_FORM:
  2248				rel.Type = objabi.R_ADDRPOWER
  2249			case DS_FORM:
  2250				rel.Type = objabi.R_ADDRPOWER_DS
  2251			}
  2252		}
  2253		return
  2254	}
  2255	
  2256	/*
  2257	 * 32-bit masks
  2258	 */
  2259	func getmask(m []byte, v uint32) bool {
  2260		m[1] = 0
  2261		m[0] = m[1]
  2262		if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */
  2263			if getmask(m, ^v) {
  2264				i := int(m[0])
  2265				m[0] = m[1] + 1
  2266				m[1] = byte(i - 1)
  2267				return true
  2268			}
  2269	
  2270			return false
  2271		}
  2272	
  2273		for i := 0; i < 32; i++ {
  2274			if v&(1<<uint(31-i)) != 0 {
  2275				m[0] = byte(i)
  2276				for {
  2277					m[1] = byte(i)
  2278					i++
  2279					if i >= 32 || v&(1<<uint(31-i)) == 0 {
  2280						break
  2281					}
  2282				}
  2283	
  2284				for ; i < 32; i++ {
  2285					if v&(1<<uint(31-i)) != 0 {
  2286						return false
  2287					}
  2288				}
  2289				return true
  2290			}
  2291		}
  2292	
  2293		return false
  2294	}
  2295	
  2296	func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) {
  2297		if !getmask(m, v) {
  2298			c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
  2299		}
  2300	}
  2301	
  2302	/*
  2303	 * 64-bit masks (rldic etc)
  2304	 */
  2305	func getmask64(m []byte, v uint64) bool {
  2306		m[1] = 0
  2307		m[0] = m[1]
  2308		for i := 0; i < 64; i++ {
  2309			if v&(uint64(1)<<uint(63-i)) != 0 {
  2310				m[0] = byte(i)
  2311				for {
  2312					m[1] = byte(i)
  2313					i++
  2314					if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 {
  2315						break
  2316					}
  2317				}
  2318	
  2319				for ; i < 64; i++ {
  2320					if v&(uint64(1)<<uint(63-i)) != 0 {
  2321						return false
  2322					}
  2323				}
  2324				return true
  2325			}
  2326		}
  2327	
  2328		return false
  2329	}
  2330	
  2331	func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) {
  2332		if !getmask64(m, v) {
  2333			c.ctxt.Diag("cannot generate mask #%x\n%v", v, p)
  2334		}
  2335	}
  2336	
  2337	func loadu32(r int, d int64) uint32 {
  2338		v := int32(d >> 16)
  2339		if isuint32(uint64(d)) {
  2340			return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
  2341		}
  2342		return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
  2343	}
  2344	
  2345	func high16adjusted(d int32) uint16 {
  2346		if d&0x8000 != 0 {
  2347			return uint16((d >> 16) + 1)
  2348		}
  2349		return uint16(d >> 16)
  2350	}
  2351	
  2352	func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) {
  2353		o1 := uint32(0)
  2354		o2 := uint32(0)
  2355		o3 := uint32(0)
  2356		o4 := uint32(0)
  2357		o5 := uint32(0)
  2358	
  2359		//print("%v => case %d\n", p, o->type);
  2360		switch o.type_ {
  2361		default:
  2362			c.ctxt.Diag("unknown type %d", o.type_)
  2363			prasm(p)
  2364	
  2365		case 0: /* pseudo ops */
  2366			if p.As == obj.APCALIGN {
  2367				aln := c.vregoff(&p.From)
  2368				v := addpad(p.Pc, aln, c.ctxt)
  2369				if v > 0 {
  2370					for i := 0; i < 6; i++ {
  2371						out[i] = uint32(0)
  2372					}
  2373					o.size = int8(v)
  2374					out[0] = LOP_RRR(OP_OR, REGZERO, REGZERO, REGZERO)
  2375					return
  2376				}
  2377				o.size = 0
  2378			}
  2379			break
  2380	
  2381		case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */
  2382			if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST {
  2383				v := c.regoff(&p.From)
  2384				if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 {
  2385					//nerrors--;
  2386					c.ctxt.Diag("literal operation on R0\n%v", p)
  2387				}
  2388	
  2389				o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v))
  2390				break
  2391			}
  2392	
  2393			o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
  2394	
  2395		case 2: /* int/cr/fp op Rb,[Ra],Rd */
  2396			r := int(p.Reg)
  2397	
  2398			if r == 0 {
  2399				r = int(p.To.Reg)
  2400			}
  2401			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2402	
  2403		case 3: /* mov $soreg/addcon/andcon/ucon, r ==> addis/oris/addi/ori $i,reg',r */
  2404			d := c.vregoff(&p.From)
  2405	
  2406			v := int32(d)
  2407			r := int(p.From.Reg)
  2408			if r == 0 {
  2409				r = int(o.param)
  2410			}
  2411			if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) {
  2412				c.ctxt.Diag("literal operation on R0\n%v", p)
  2413			}
  2414			a := OP_ADDI
  2415			if o.a1 == C_UCON {
  2416				if d&0xffff != 0 {
  2417					log.Fatalf("invalid handling of %v", p)
  2418				}
  2419				// For UCON operands the value is right shifted 16, using ADDIS if the
  2420				// value should be signed, ORIS if unsigned.
  2421				v >>= 16
  2422				if r == REGZERO && isuint32(uint64(d)) {
  2423					o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v))
  2424					break
  2425				}
  2426	
  2427				a = OP_ADDIS
  2428			} else if int64(int16(d)) != d {
  2429				// Operand is 16 bit value with sign bit set
  2430				if o.a1 == C_ANDCON {
  2431					// Needs unsigned 16 bit so use ORI
  2432					if r == 0 || r == REGZERO {
  2433						o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
  2434						break
  2435					}
  2436					// With ADDCON, needs signed 16 bit value, fall through to use ADDI
  2437				} else if o.a1 != C_ADDCON {
  2438					log.Fatalf("invalid handling of %v", p)
  2439				}
  2440			}
  2441	
  2442			o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v))
  2443	
  2444		case 4: /* add/mul $scon,[r1],r2 */
  2445			v := c.regoff(&p.From)
  2446	
  2447			r := int(p.Reg)
  2448			if r == 0 {
  2449				r = int(p.To.Reg)
  2450			}
  2451			if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 {
  2452				c.ctxt.Diag("literal operation on R0\n%v", p)
  2453			}
  2454			if int32(int16(v)) != v {
  2455				log.Fatalf("mishandled instruction %v", p)
  2456			}
  2457			o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2458	
  2459		case 5: /* syscall */
  2460			o1 = c.oprrr(p.As)
  2461	
  2462		case 6: /* logical op Rb,[Rs,]Ra; no literal */
  2463			r := int(p.Reg)
  2464	
  2465			if r == 0 {
  2466				r = int(p.To.Reg)
  2467			}
  2468			// AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM.
  2469			switch p.As {
  2470			case AROTL:
  2471				o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
  2472			case AROTLW:
  2473				o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
  2474			default:
  2475				o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2476			}
  2477	
  2478		case 7: /* mov r, soreg ==> stw o(r) */
  2479			r := int(p.To.Reg)
  2480	
  2481			if r == 0 {
  2482				r = int(o.param)
  2483			}
  2484			v := c.regoff(&p.To)
  2485			if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 {
  2486				if v != 0 {
  2487					c.ctxt.Diag("illegal indexed instruction\n%v", p)
  2488				}
  2489				if c.ctxt.Flag_shared && r == REG_R13 {
  2490					rel := obj.Addrel(c.cursym)
  2491					rel.Off = int32(c.pc)
  2492					rel.Siz = 4
  2493					// This (and the matching part in the load case
  2494					// below) are the only places in the ppc64 toolchain
  2495					// that knows the name of the tls variable. Possibly
  2496					// we could add some assembly syntax so that the name
  2497					// of the variable does not have to be assumed.
  2498					rel.Sym = c.ctxt.Lookup("runtime.tls_g")
  2499					rel.Type = objabi.R_POWER_TLS
  2500				}
  2501				o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
  2502			} else {
  2503				if int32(int16(v)) != v {
  2504					log.Fatalf("mishandled instruction %v", p)
  2505				}
  2506				// Offsets in DS form stores must be a multiple of 4
  2507				inst := c.opstore(p.As)
  2508				if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2509					log.Fatalf("invalid offset for DS form load/store %v", p)
  2510				}
  2511				o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
  2512			}
  2513	
  2514		case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */
  2515			r := int(p.From.Reg)
  2516	
  2517			if r == 0 {
  2518				r = int(o.param)
  2519			}
  2520			v := c.regoff(&p.From)
  2521			if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
  2522				if v != 0 {
  2523					c.ctxt.Diag("illegal indexed instruction\n%v", p)
  2524				}
  2525				if c.ctxt.Flag_shared && r == REG_R13 {
  2526					rel := obj.Addrel(c.cursym)
  2527					rel.Off = int32(c.pc)
  2528					rel.Siz = 4
  2529					rel.Sym = c.ctxt.Lookup("runtime.tls_g")
  2530					rel.Type = objabi.R_POWER_TLS
  2531				}
  2532				o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
  2533			} else {
  2534				if int32(int16(v)) != v {
  2535					log.Fatalf("mishandled instruction %v", p)
  2536				}
  2537				// Offsets in DS form loads must be a multiple of 4
  2538				inst := c.opload(p.As)
  2539				if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  2540					log.Fatalf("invalid offset for DS form load/store %v", p)
  2541				}
  2542				o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
  2543			}
  2544	
  2545		case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */
  2546			r := int(p.From.Reg)
  2547	
  2548			if r == 0 {
  2549				r = int(o.param)
  2550			}
  2551			v := c.regoff(&p.From)
  2552			if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 {
  2553				if v != 0 {
  2554					c.ctxt.Diag("illegal indexed instruction\n%v", p)
  2555				}
  2556				o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
  2557			} else {
  2558				o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2559			}
  2560			o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  2561	
  2562		case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */
  2563			r := int(p.Reg)
  2564	
  2565			if r == 0 {
  2566				r = int(p.To.Reg)
  2567			}
  2568			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
  2569	
  2570		case 11: /* br/bl lbra */
  2571			v := int32(0)
  2572	
  2573			if p.Pcond != nil {
  2574				v = int32(p.Pcond.Pc - p.Pc)
  2575				if v&03 != 0 {
  2576					c.ctxt.Diag("odd branch target address\n%v", p)
  2577					v &^= 03
  2578				}
  2579	
  2580				if v < -(1<<25) || v >= 1<<24 {
  2581					c.ctxt.Diag("branch too far\n%v", p)
  2582				}
  2583			}
  2584	
  2585			o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
  2586			if p.To.Sym != nil {
  2587				rel := obj.Addrel(c.cursym)
  2588				rel.Off = int32(c.pc)
  2589				rel.Siz = 4
  2590				rel.Sym = p.To.Sym
  2591				v += int32(p.To.Offset)
  2592				if v&03 != 0 {
  2593					c.ctxt.Diag("odd branch target address\n%v", p)
  2594					v &^= 03
  2595				}
  2596	
  2597				rel.Add = int64(v)
  2598				rel.Type = objabi.R_CALLPOWER
  2599			}
  2600			o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking
  2601	
  2602		case 12: /* movb r,r (extsb); movw r,r (extsw) */
  2603			if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST {
  2604				v := c.regoff(&p.From)
  2605				if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 {
  2606					c.ctxt.Diag("literal operation on R0\n%v", p)
  2607				}
  2608	
  2609				o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v))
  2610				break
  2611			}
  2612	
  2613			if p.As == AMOVW {
  2614				o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2615			} else {
  2616				o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2617			}
  2618	
  2619		case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */
  2620			if p.As == AMOVBZ {
  2621				o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
  2622			} else if p.As == AMOVH {
  2623				o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
  2624			} else if p.As == AMOVHZ {
  2625				o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
  2626			} else if p.As == AMOVWZ {
  2627				o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */
  2628			} else {
  2629				c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p)
  2630			}
  2631	
  2632		case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */
  2633			r := int(p.Reg)
  2634	
  2635			if r == 0 {
  2636				r = int(p.To.Reg)
  2637			}
  2638			d := c.vregoff(p.GetFrom3())
  2639			var a int
  2640			switch p.As {
  2641	
  2642			// These opcodes expect a mask operand that has to be converted into the
  2643			// appropriate operand.  The way these were defined, not all valid masks are possible.
  2644			// Left here for compatibility in case they were used or generated.
  2645			case ARLDCL, ARLDCLCC:
  2646				var mask [2]uint8
  2647				c.maskgen64(p, mask[:], uint64(d))
  2648	
  2649				a = int(mask[0]) /* MB */
  2650				if mask[1] != 63 {
  2651					c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
  2652				}
  2653				o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2654				o1 |= (uint32(a) & 31) << 6
  2655				if a&0x20 != 0 {
  2656					o1 |= 1 << 5 /* mb[5] is top bit */
  2657				}
  2658	
  2659			case ARLDCR, ARLDCRCC:
  2660				var mask [2]uint8
  2661				c.maskgen64(p, mask[:], uint64(d))
  2662	
  2663				a = int(mask[1]) /* ME */
  2664				if mask[0] != 0 {
  2665					c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
  2666				}
  2667				o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
  2668				o1 |= (uint32(a) & 31) << 6
  2669				if a&0x20 != 0 {
  2670					o1 |= 1 << 5 /* mb[5] is top bit */
  2671				}
  2672	
  2673			// These opcodes use a shift count like the ppc64 asm, no mask conversion done
  2674			case ARLDICR, ARLDICRCC:
  2675				me := int(d)
  2676				sh := c.regoff(&p.From)
  2677				o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me))
  2678	
  2679			case ARLDICL, ARLDICLCC:
  2680				mb := int(d)
  2681				sh := c.regoff(&p.From)
  2682				o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb))
  2683	
  2684			default:
  2685				c.ctxt.Diag("unexpected op in rldc case\n%v", p)
  2686				a = 0
  2687			}
  2688	
  2689		case 17, /* bc bo,bi,lbra (same for now) */
  2690			16: /* bc bo,bi,sbra */
  2691			a := 0
  2692	
  2693			r := int(p.Reg)
  2694	
  2695			if p.From.Type == obj.TYPE_CONST {
  2696				a = int(c.regoff(&p.From))
  2697			} else if p.From.Type == obj.TYPE_REG {
  2698				if r != 0 {
  2699					c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
  2700				}
  2701				// BI values for the CR
  2702				switch p.From.Reg {
  2703				case REG_CR0:
  2704					r = BI_CR0
  2705				case REG_CR1:
  2706					r = BI_CR1
  2707				case REG_CR2:
  2708					r = BI_CR2
  2709				case REG_CR3:
  2710					r = BI_CR3
  2711				case REG_CR4:
  2712					r = BI_CR4
  2713				case REG_CR5:
  2714					r = BI_CR5
  2715				case REG_CR6:
  2716					r = BI_CR6
  2717				case REG_CR7:
  2718					r = BI_CR7
  2719				default:
  2720					c.ctxt.Diag("unrecognized register: expecting CR\n")
  2721				}
  2722			}
  2723			v := int32(0)
  2724			if p.Pcond != nil {
  2725				v = int32(p.Pcond.Pc - p.Pc)
  2726			}
  2727			if v&03 != 0 {
  2728				c.ctxt.Diag("odd branch target address\n%v", p)
  2729				v &^= 03
  2730			}
  2731	
  2732			if v < -(1<<16) || v >= 1<<15 {
  2733				c.ctxt.Diag("branch too far\n%v", p)
  2734			}
  2735			o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
  2736	
  2737		case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */
  2738			var v int32
  2739			if p.As == ABC || p.As == ABCL {
  2740				v = c.regoff(&p.To) & 31
  2741			} else {
  2742				v = 20 /* unconditional */
  2743			}
  2744			o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11
  2745			o2 = OPVCC(19, 16, 0, 0)
  2746			if p.As == ABL || p.As == ABCL {
  2747				o2 |= 1
  2748			}
  2749			o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index))
  2750	
  2751		case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */
  2752			var v int32
  2753			if p.As == ABC || p.As == ABCL {
  2754				v = c.regoff(&p.From) & 31
  2755			} else {
  2756				v = 20 /* unconditional */
  2757			}
  2758			r := int(p.Reg)
  2759			if r == 0 {
  2760				r = 0
  2761			}
  2762			switch oclass(&p.To) {
  2763			case C_CTR:
  2764				o1 = OPVCC(19, 528, 0, 0)
  2765	
  2766			case C_LR:
  2767				o1 = OPVCC(19, 16, 0, 0)
  2768	
  2769			default:
  2770				c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
  2771				v = 0
  2772			}
  2773	
  2774			if p.As == ABL || p.As == ABCL {
  2775				o1 |= 1
  2776			}
  2777			o1 = OP_BCR(o1, uint32(v), uint32(r))
  2778	
  2779		case 19: /* mov $lcon,r ==> cau+or */
  2780			d := c.vregoff(&p.From)
  2781	
  2782			if p.From.Sym == nil {
  2783				o1 = loadu32(int(p.To.Reg), d)
  2784				o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
  2785			} else {
  2786				o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI)
  2787			}
  2788	
  2789		case 20: /* add $ucon,,r | addis $addcon,r,r */
  2790			v := c.regoff(&p.From)
  2791	
  2792			r := int(p.Reg)
  2793			if r == 0 {
  2794				r = int(p.To.Reg)
  2795			}
  2796			if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) {
  2797				c.ctxt.Diag("literal operation on R0\n%v", p)
  2798			}
  2799			if p.As == AADDIS {
  2800				o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2801			} else {
  2802				o1 = AOP_IRR(c.opirr(AADDIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
  2803			}
  2804	
  2805		case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add */
  2806			if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2807				c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2808			}
  2809			d := c.vregoff(&p.From)
  2810			r := int(p.Reg)
  2811			if r == 0 {
  2812				r = int(p.To.Reg)
  2813			}
  2814			if p.From.Sym != nil {
  2815				c.ctxt.Diag("%v is not supported", p)
  2816			}
  2817			// If operand is ANDCON, generate 2 instructions using
  2818			// ORI for unsigned value; with LCON 3 instructions.
  2819			if o.size == 8 {
  2820				o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
  2821				o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2822			} else {
  2823				o1 = loadu32(REGTMP, d)
  2824				o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
  2825				o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2826			}
  2827	
  2828		case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */
  2829			if p.To.Reg == REGTMP || p.Reg == REGTMP {
  2830				c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2831			}
  2832			d := c.vregoff(&p.From)
  2833			r := int(p.Reg)
  2834			if r == 0 {
  2835				r = int(p.To.Reg)
  2836			}
  2837	
  2838			// With ADDCON operand, generate 2 instructions using ADDI for signed value,
  2839			// with LCON operand generate 3 instructions.
  2840			if o.size == 8 {
  2841				o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
  2842				o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2843			} else {
  2844				o1 = loadu32(REGTMP, d)
  2845				o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d)))
  2846				o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
  2847			}
  2848			if p.From.Sym != nil {
  2849				c.ctxt.Diag("%v is not supported", p)
  2850			}
  2851	
  2852		case 24: /* lfd fA,float64(0) -> xxlxor xsA,xsaA,xsaA + fneg for -0 */
  2853			o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
  2854			// This is needed for -0.
  2855			if o.size == 8 {
  2856				o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
  2857			}
  2858	
  2859		case 25:
  2860			/* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */
  2861			v := c.regoff(&p.From)
  2862	
  2863			if v < 0 {
  2864				v = 0
  2865			} else if v > 63 {
  2866				v = 63
  2867			}
  2868			r := int(p.Reg)
  2869			if r == 0 {
  2870				r = int(p.To.Reg)
  2871			}
  2872			var a int
  2873			op := uint32(0)
  2874			switch p.As {
  2875			case ASLD, ASLDCC:
  2876				a = int(63 - v)
  2877				op = OP_RLDICR
  2878	
  2879			case ASRD, ASRDCC:
  2880				a = int(v)
  2881				v = 64 - v
  2882				op = OP_RLDICL
  2883			case AROTL:
  2884				a = int(0)
  2885				op = OP_RLDICL
  2886			default:
  2887				c.ctxt.Diag("unexpected op in sldi case\n%v", p)
  2888				a = 0
  2889				o1 = 0
  2890			}
  2891	
  2892			o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
  2893			if p.As == ASLDCC || p.As == ASRDCC {
  2894				o1 |= 1 // Set the condition code bit
  2895			}
  2896	
  2897		case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */
  2898			if p.To.Reg == REGTMP {
  2899				c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2900			}
  2901			v := c.regoff(&p.From)
  2902			r := int(p.From.Reg)
  2903			if r == 0 {
  2904				r = int(o.param)
  2905			}
  2906			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  2907			o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v))
  2908	
  2909		case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */
  2910			v := c.regoff(p.GetFrom3())
  2911	
  2912			r := int(p.From.Reg)
  2913			o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  2914	
  2915		case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */
  2916			if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
  2917				c.ctxt.Diag("can't synthesize large constant\n%v", p)
  2918			}
  2919			v := c.regoff(p.GetFrom3())
  2920			o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
  2921			o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v))
  2922			o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
  2923			if p.From.Sym != nil {
  2924				c.ctxt.Diag("%v is not supported", p)
  2925			}
  2926	
  2927		//if(dlm) reloc(&p->from3, p->pc, 0);
  2928	
  2929		case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */
  2930			v := c.regoff(&p.From)
  2931	
  2932			d := c.vregoff(p.GetFrom3())
  2933			var mask [2]uint8
  2934			c.maskgen64(p, mask[:], uint64(d))
  2935			var a int
  2936			switch p.As {
  2937			case ARLDC, ARLDCCC:
  2938				a = int(mask[0]) /* MB */
  2939				if int32(mask[1]) != (63 - v) {
  2940					c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p)
  2941				}
  2942	
  2943			case ARLDCL, ARLDCLCC:
  2944				a = int(mask[0]) /* MB */
  2945				if mask[1] != 63 {
  2946					c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p)
  2947				}
  2948	
  2949			case ARLDCR, ARLDCRCC:
  2950				a = int(mask[1]) /* ME */
  2951				if mask[0] != 0 {
  2952					c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p)
  2953				}
  2954	
  2955			default:
  2956				c.ctxt.Diag("unexpected op in rldic case\n%v", p)
  2957				a = 0
  2958			}
  2959	
  2960			o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
  2961			o1 |= (uint32(a) & 31) << 6
  2962			if v&0x20 != 0 {
  2963				o1 |= 1 << 1
  2964			}
  2965			if a&0x20 != 0 {
  2966				o1 |= 1 << 5 /* mb[5] is top bit */
  2967			}
  2968	
  2969		case 30: /* rldimi $sh,s,$mask,a */
  2970			v := c.regoff(&p.From)
  2971	
  2972			d := c.vregoff(p.GetFrom3())
  2973	
  2974			// Original opcodes had mask operands which had to be converted to a shift count as expected by
  2975			// the ppc64 asm.
  2976			switch p.As {
  2977			case ARLDMI, ARLDMICC:
  2978				var mask [2]uint8
  2979				c.maskgen64(p, mask[:], uint64(d))
  2980				if int32(mask[1]) != (63 - v) {
  2981					c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p)
  2982				}
  2983				o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
  2984				o1 |= (uint32(mask[0]) & 31) << 6
  2985				if v&0x20 != 0 {
  2986					o1 |= 1 << 1
  2987				}
  2988				if mask[0]&0x20 != 0 {
  2989					o1 |= 1 << 5 /* mb[5] is top bit */
  2990				}
  2991	
  2992			// Opcodes with shift count operands.
  2993			case ARLDIMI, ARLDIMICC:
  2994				o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F))
  2995				o1 |= (uint32(d) & 31) << 6
  2996				if d&0x20 != 0 {
  2997					o1 |= 1 << 5
  2998				}
  2999				if v&0x20 != 0 {
  3000					o1 |= 1 << 1
  3001				}
  3002			}
  3003	
  3004		case 31: /* dword */
  3005			d := c.vregoff(&p.From)
  3006	
  3007			if c.ctxt.Arch.ByteOrder == binary.BigEndian {
  3008				o1 = uint32(d >> 32)
  3009				o2 = uint32(d)
  3010			} else {
  3011				o1 = uint32(d)
  3012				o2 = uint32(d >> 32)
  3013			}
  3014	
  3015			if p.From.Sym != nil {
  3016				rel := obj.Addrel(c.cursym)
  3017				rel.Off = int32(c.pc)
  3018				rel.Siz = 8
  3019				rel.Sym = p.From.Sym
  3020				rel.Add = p.From.Offset
  3021				rel.Type = objabi.R_ADDR
  3022				o2 = 0
  3023				o1 = o2
  3024			}
  3025	
  3026		case 32: /* fmul frc,fra,frd */
  3027			r := int(p.Reg)
  3028	
  3029			if r == 0 {
  3030				r = int(p.To.Reg)
  3031			}
  3032			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
  3033	
  3034		case 33: /* fabs [frb,]frd; fmr. frb,frd */
  3035			r := int(p.From.Reg)
  3036	
  3037			if oclass(&p.From) == C_NONE {
  3038				r = int(p.To.Reg)
  3039			}
  3040			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
  3041	
  3042		case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */
  3043			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
  3044	
  3045		case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */
  3046			v := c.regoff(&p.To)
  3047	
  3048			r := int(p.To.Reg)
  3049			if r == 0 {
  3050				r = int(o.param)
  3051			}
  3052			// Offsets in DS form stores must be a multiple of 4
  3053			inst := c.opstore(p.As)
  3054			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3055				log.Fatalf("invalid offset for DS form load/store %v", p)
  3056			}
  3057			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  3058			o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
  3059	
  3060		case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */
  3061			v := c.regoff(&p.From)
  3062	
  3063			r := int(p.From.Reg)
  3064			if r == 0 {
  3065				r = int(o.param)
  3066			}
  3067			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  3068			o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v))
  3069	
  3070		case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */
  3071			v := c.regoff(&p.From)
  3072	
  3073			r := int(p.From.Reg)
  3074			if r == 0 {
  3075				r = int(o.param)
  3076			}
  3077			o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
  3078			o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v))
  3079			o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3080	
  3081		case 40: /* word */
  3082			o1 = uint32(c.regoff(&p.From))
  3083	
  3084		case 41: /* stswi */
  3085			o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3086	
  3087		case 42: /* lswi */
  3088			o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
  3089	
  3090		case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */
  3091			/* TH field for dcbt/dcbtst: */
  3092			/* 0 = Block access - program will soon access EA. */
  3093			/* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */
  3094			/* 16 = Block access - program will soon make a transient access to EA. */
  3095			/* 17 = Block access - program will not access EA for a long time. */
  3096	
  3097			/* L field for dcbf: */
  3098			/* 0 = invalidates the block containing EA in all processors. */
  3099			/* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */
  3100			/* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */
  3101			if p.To.Type == obj.TYPE_NONE {
  3102				o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
  3103			} else {
  3104				th := c.regoff(&p.To)
  3105				o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
  3106			}
  3107	
  3108		case 44: /* indexed store */
  3109			o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3110	
  3111		case 45: /* indexed load */
  3112			switch p.As {
  3113			/* The assembler accepts a 4-operand l*arx instruction. The fourth operand is an Exclusive Access Hint (EH) */
  3114			/* The EH field can be used as a lock acquire/release hint as follows: */
  3115			/* 0 = Atomic Update (fetch-and-operate or similar algorithm) */
  3116			/* 1 = Exclusive Access (lock acquire and release) */
  3117			case ALBAR, ALHAR, ALWAR, ALDAR:
  3118				if p.From3Type() != obj.TYPE_NONE {
  3119					eh := int(c.regoff(p.GetFrom3()))
  3120					if eh > 1 {
  3121						c.ctxt.Diag("illegal EH field\n%v", p)
  3122					}
  3123					o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
  3124				} else {
  3125					o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3126				}
  3127			default:
  3128				o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3129			}
  3130		case 46: /* plain op */
  3131			o1 = c.oprrr(p.As)
  3132	
  3133		case 47: /* op Ra, Rd; also op [Ra,] Rd */
  3134			r := int(p.From.Reg)
  3135	
  3136			if r == 0 {
  3137				r = int(p.To.Reg)
  3138			}
  3139			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3140	
  3141		case 48: /* op Rs, Ra */
  3142			r := int(p.From.Reg)
  3143	
  3144			if r == 0 {
  3145				r = int(p.To.Reg)
  3146			}
  3147			o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
  3148	
  3149		case 49: /* op Rb; op $n, Rb */
  3150			if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */
  3151				v := c.regoff(&p.From) & 1
  3152				o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
  3153			} else {
  3154				o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
  3155			}
  3156	
  3157		case 50: /* rem[u] r1[,r2],r3 */
  3158			r := int(p.Reg)
  3159	
  3160			if r == 0 {
  3161				r = int(p.To.Reg)
  3162			}
  3163			v := c.oprrr(p.As)
  3164			t := v & (1<<10 | 1) /* OE|Rc */
  3165			o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3166			o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
  3167			o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3168			if p.As == AREMU {
  3169				o4 = o3
  3170	
  3171				/* Clear top 32 bits */
  3172				o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
  3173			}
  3174	
  3175		case 51: /* remd[u] r1[,r2],r3 */
  3176			r := int(p.Reg)
  3177	
  3178			if r == 0 {
  3179				r = int(p.To.Reg)
  3180			}
  3181			v := c.oprrr(p.As)
  3182			t := v & (1<<10 | 1) /* OE|Rc */
  3183			o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
  3184			o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
  3185			o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
  3186	
  3187		case 52: /* mtfsbNx cr(n) */
  3188			v := c.regoff(&p.From) & 31
  3189	
  3190			o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
  3191	
  3192		case 53: /* mffsX ,fr1 */
  3193			o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
  3194	
  3195		case 54: /* mov msr,r1; mov r1, msr*/
  3196			if oclass(&p.From) == C_REG {
  3197				if p.As == AMOVD {
  3198					o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0)
  3199				} else {
  3200					o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0)
  3201				}
  3202			} else {
  3203				o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0)
  3204			}
  3205	
  3206		case 55: /* op Rb, Rd */
  3207			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
  3208	
  3209		case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */
  3210			v := c.regoff(&p.From)
  3211	
  3212			r := int(p.Reg)
  3213			if r == 0 {
  3214				r = int(p.To.Reg)
  3215			}
  3216			o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
  3217			if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
  3218				o1 |= 1 << 1 /* mb[5] */
  3219			}
  3220	
  3221		case 57: /* slw $sh,[s,]a -> rlwinm ... */
  3222			v := c.regoff(&p.From)
  3223	
  3224			r := int(p.Reg)
  3225			if r == 0 {
  3226				r = int(p.To.Reg)
  3227			}
  3228	
  3229			/*
  3230				 * Let user (gs) shoot himself in the foot.
  3231				 * qc has already complained.
  3232				 *
  3233				if(v < 0 || v > 31)
  3234					ctxt->diag("illegal shift %ld\n%v", v, p);
  3235			*/
  3236			if v < 0 {
  3237				v = 0
  3238			} else if v > 32 {
  3239				v = 32
  3240			}
  3241			var mask [2]uint8
  3242			switch p.As {
  3243			case AROTLW:
  3244				mask[0], mask[1] = 0, 31
  3245			case ASRW, ASRWCC:
  3246				mask[0], mask[1] = uint8(v), 31
  3247				v = 32 - v
  3248			default:
  3249				mask[0], mask[1] = 0, uint8(31-v)
  3250			}
  3251			o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
  3252			if p.As == ASLWCC || p.As == ASRWCC {
  3253				o1 |= 1 // set the condition code
  3254			}
  3255	
  3256		case 58: /* logical $andcon,[s],a */
  3257			v := c.regoff(&p.From)
  3258	
  3259			r := int(p.Reg)
  3260			if r == 0 {
  3261				r = int(p.To.Reg)
  3262			}
  3263			o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3264	
  3265		case 59: /* or/xor/and $ucon,,r | oris/xoris/andis $addcon,r,r */
  3266			v := c.regoff(&p.From)
  3267	
  3268			r := int(p.Reg)
  3269			if r == 0 {
  3270				r = int(p.To.Reg)
  3271			}
  3272			switch p.As {
  3273			case AOR:
  3274				o1 = LOP_IRR(c.opirr(AORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis. */
  3275			case AXOR:
  3276				o1 = LOP_IRR(c.opirr(AXORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
  3277			case AANDCC:
  3278				o1 = LOP_IRR(c.opirr(AANDISCC), uint32(p.To.Reg), uint32(r), uint32(v)>>16)
  3279			default:
  3280				o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
  3281			}
  3282	
  3283		case 60: /* tw to,a,b */
  3284			r := int(c.regoff(&p.From) & 31)
  3285	
  3286			o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
  3287	
  3288		case 61: /* tw to,a,$simm */
  3289			r := int(c.regoff(&p.From) & 31)
  3290	
  3291			v := c.regoff(&p.To)
  3292			o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
  3293	
  3294		case 62: /* rlwmi $sh,s,$mask,a */
  3295			v := c.regoff(&p.From)
  3296	
  3297			var mask [2]uint8
  3298			c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
  3299			o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v))
  3300			o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
  3301	
  3302		case 63: /* rlwmi b,s,$mask,a */
  3303			var mask [2]uint8
  3304			c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3())))
  3305	
  3306			o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg))
  3307			o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1
  3308	
  3309		case 64: /* mtfsf fr[, $m] {,fpcsr} */
  3310			var v int32
  3311			if p.From3Type() != obj.TYPE_NONE {
  3312				v = c.regoff(p.GetFrom3()) & 255
  3313			} else {
  3314				v = 255
  3315			}
  3316			o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
  3317	
  3318		case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */
  3319			if p.To.Reg == 0 {
  3320				c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
  3321			}
  3322			o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
  3323	
  3324		case 66: /* mov spr,r1; mov r1,spr, also dcr */
  3325			var r int
  3326			var v int32
  3327			if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
  3328				r = int(p.From.Reg)
  3329				v = int32(p.To.Reg)
  3330				if REG_DCR0 <= v && v <= REG_DCR0+1023 {
  3331					o1 = OPVCC(31, 451, 0, 0) /* mtdcr */
  3332				} else {
  3333					o1 = OPVCC(31, 467, 0, 0) /* mtspr */
  3334				}
  3335			} else {
  3336				r = int(p.To.Reg)
  3337				v = int32(p.From.Reg)
  3338				if REG_DCR0 <= v && v <= REG_DCR0+1023 {
  3339					o1 = OPVCC(31, 323, 0, 0) /* mfdcr */
  3340				} else {
  3341					o1 = OPVCC(31, 339, 0, 0) /* mfspr */
  3342				}
  3343			}
  3344	
  3345			o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
  3346	
  3347		case 67: /* mcrf crfD,crfS */
  3348			if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
  3349				c.ctxt.Diag("illegal CR field number\n%v", p)
  3350			}
  3351			o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
  3352	
  3353		case 68: /* mfcr rD; mfocrf CRM,rD */
  3354			if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 {
  3355				v := int32(1 << uint(7-(p.To.Reg&7)))                                 /* CR(n) */
  3356				o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */
  3357			} else {
  3358				o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */
  3359			}
  3360	
  3361		case 69: /* mtcrf CRM,rS */
  3362			var v int32
  3363			if p.From3Type() != obj.TYPE_NONE {
  3364				if p.To.Reg != 0 {
  3365					c.ctxt.Diag("can't use both mask and CR(n)\n%v", p)
  3366				}
  3367				v = c.regoff(p.GetFrom3()) & 0xff
  3368			} else {
  3369				if p.To.Reg == 0 {
  3370					v = 0xff /* CR */
  3371				} else {
  3372					v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */
  3373				}
  3374			}
  3375	
  3376			o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
  3377	
  3378		case 70: /* [f]cmp r,r,cr*/
  3379			var r int
  3380			if p.Reg == 0 {
  3381				r = 0
  3382			} else {
  3383				r = (int(p.Reg) & 7) << 2
  3384			}
  3385			o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg))
  3386	
  3387		case 71: /* cmp[l] r,i,cr*/
  3388			var r int
  3389			if p.Reg == 0 {
  3390				r = 0
  3391			} else {
  3392				r = (int(p.Reg) & 7) << 2
  3393			}
  3394			o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff
  3395	
  3396		case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */
  3397			o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
  3398	
  3399		case 73: /* mcrfs crfD,crfS */
  3400			if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
  3401				c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
  3402			}
  3403			o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
  3404	
  3405		case 77: /* syscall $scon, syscall Rx */
  3406			if p.From.Type == obj.TYPE_CONST {
  3407				if p.From.Offset > BIG || p.From.Offset < -BIG {
  3408					c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
  3409				}
  3410				o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
  3411			} else if p.From.Type == obj.TYPE_REG {
  3412				o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
  3413			} else {
  3414				c.ctxt.Diag("illegal syscall: %v", p)
  3415				o1 = 0x7fe00008 // trap always
  3416			}
  3417	
  3418			o2 = c.oprrr(p.As)
  3419			o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0
  3420	
  3421		case 78: /* undef */
  3422			o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed
  3423			   always to be an illegal instruction."  */
  3424	
  3425		/* relocation operations */
  3426		case 74:
  3427			v := c.vregoff(&p.To)
  3428			// Offsets in DS form stores must be a multiple of 4
  3429			inst := c.opstore(p.As)
  3430			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3431				log.Fatalf("invalid offset for DS form load/store %v", p)
  3432			}
  3433			o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst)
  3434	
  3435		//if(dlm) reloc(&p->to, p->pc, 1);
  3436	
  3437		case 75:
  3438			v := c.vregoff(&p.From)
  3439			// Offsets in DS form loads must be a multiple of 4
  3440			inst := c.opload(p.As)
  3441			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3442				log.Fatalf("invalid offset for DS form load/store %v", p)
  3443			}
  3444			o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst)
  3445	
  3446		//if(dlm) reloc(&p->from, p->pc, 1);
  3447	
  3448		case 76:
  3449			v := c.vregoff(&p.From)
  3450			// Offsets in DS form loads must be a multiple of 4
  3451			inst := c.opload(p.As)
  3452			if c.opform(inst) == DS_FORM && v&0x3 != 0 {
  3453				log.Fatalf("invalid offset for DS form load/store %v", p)
  3454			}
  3455			o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst)
  3456			o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3457	
  3458			//if(dlm) reloc(&p->from, p->pc, 1);
  3459	
  3460		case 79:
  3461			if p.From.Offset != 0 {
  3462				c.ctxt.Diag("invalid offset against tls var %v", p)
  3463			}
  3464			o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0)
  3465			rel := obj.Addrel(c.cursym)
  3466			rel.Off = int32(c.pc)
  3467			rel.Siz = 4
  3468			rel.Sym = p.From.Sym
  3469			rel.Type = objabi.R_POWER_TLS_LE
  3470	
  3471		case 80:
  3472			if p.From.Offset != 0 {
  3473				c.ctxt.Diag("invalid offset against tls var %v", p)
  3474			}
  3475			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3476			o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3477			rel := obj.Addrel(c.cursym)
  3478			rel.Off = int32(c.pc)
  3479			rel.Siz = 8
  3480			rel.Sym = p.From.Sym
  3481			rel.Type = objabi.R_POWER_TLS_IE
  3482	
  3483		case 81:
  3484			v := c.vregoff(&p.To)
  3485			if v != 0 {
  3486				c.ctxt.Diag("invalid offset against GOT slot %v", p)
  3487			}
  3488	
  3489			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3490			o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3491			rel := obj.Addrel(c.cursym)
  3492			rel.Off = int32(c.pc)
  3493			rel.Siz = 8
  3494			rel.Sym = p.From.Sym
  3495			rel.Type = objabi.R_ADDRPOWER_GOT
  3496		case 82: /* vector instructions, VX-form and VC-form */
  3497			if p.From.Type == obj.TYPE_REG {
  3498				/* reg reg none OR reg reg reg */
  3499				/* 3-register operand order: VRA, VRB, VRT */
  3500				/* 2-register operand order: VRA, VRT */
  3501				o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3502			} else if p.From3Type() == obj.TYPE_CONST {
  3503				/* imm imm reg reg */
  3504				/* operand order: SIX, VRA, ST, VRT */
  3505				six := int(c.regoff(&p.From))
  3506				st := int(c.regoff(p.GetFrom3()))
  3507				o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
  3508			} else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
  3509				/* imm reg reg */
  3510				/* operand order: UIM, VRB, VRT */
  3511				uim := int(c.regoff(&p.From))
  3512				o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
  3513			} else {
  3514				/* imm reg */
  3515				/* operand order: SIM, VRT */
  3516				sim := int(c.regoff(&p.From))
  3517				o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
  3518			}
  3519	
  3520		case 83: /* vector instructions, VA-form */
  3521			if p.From.Type == obj.TYPE_REG {
  3522				/* reg reg reg reg */
  3523				/* 4-register operand order: VRA, VRB, VRC, VRT */
  3524				o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3525			} else if p.From.Type == obj.TYPE_CONST {
  3526				/* imm reg reg reg */
  3527				/* operand order: SHB, VRA, VRB, VRT */
  3528				shb := int(c.regoff(&p.From))
  3529				o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
  3530			}
  3531	
  3532		case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc
  3533			bc := c.vregoff(&p.From)
  3534	
  3535			// rt = To.Reg, ra = p.Reg, rb = p.From3.Reg
  3536			o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
  3537	
  3538		case 85: /* vector instructions, VX-form */
  3539			/* reg none reg */
  3540			/* 2-register operand order: VRB, VRT */
  3541			o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
  3542	
  3543		case 86: /* VSX indexed store, XX1-form */
  3544			/* reg reg reg */
  3545			/* 3-register operand order: XT, (RB)(RA*1) */
  3546			o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
  3547	
  3548		case 87: /* VSX indexed load, XX1-form */
  3549			/* reg reg reg */
  3550			/* 3-register operand order: (RB)(RA*1), XT */
  3551			o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
  3552	
  3553		case 88: /* VSX instructions, XX1-form */
  3554			/* reg reg none OR reg reg reg */
  3555			/* 3-register operand order: RA, RB, XT */
  3556			/* 2-register operand order: XS, RA or RA, XT */
  3557			xt := int32(p.To.Reg)
  3558			xs := int32(p.From.Reg)
  3559			/* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */
  3560			if REG_V0 <= xt && xt <= REG_V31 {
  3561				/* Convert V0-V31 to VS32-VS63 */
  3562				xt = xt + 64
  3563				o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
  3564			} else if REG_F0 <= xt && xt <= REG_F31 {
  3565				/* Convert F0-F31 to VS0-VS31 */
  3566				xt = xt + 64
  3567				o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
  3568			} else if REG_VS0 <= xt && xt <= REG_VS63 {
  3569				o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg))
  3570			} else if REG_V0 <= xs && xs <= REG_V31 {
  3571				/* Likewise for XS */
  3572				xs = xs + 64
  3573				o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
  3574			} else if REG_F0 <= xs && xs <= REG_F31 {
  3575				xs = xs + 64
  3576				o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
  3577			} else if REG_VS0 <= xs && xs <= REG_VS63 {
  3578				o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg))
  3579			}
  3580	
  3581		case 89: /* VSX instructions, XX2-form */
  3582			/* reg none reg OR reg imm reg */
  3583			/* 2-register operand order: XB, XT or XB, UIM, XT*/
  3584			uim := int(c.regoff(p.GetFrom3()))
  3585			o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
  3586	
  3587		case 90: /* VSX instructions, XX3-form */
  3588			if p.From3Type() == obj.TYPE_NONE {
  3589				/* reg reg reg */
  3590				/* 3-register operand order: XA, XB, XT */
  3591				o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
  3592			} else if p.From3Type() == obj.TYPE_CONST {
  3593				/* reg reg reg imm */
  3594				/* operand order: XA, XB, DM, XT */
  3595				dm := int(c.regoff(p.GetFrom3()))
  3596				o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
  3597			}
  3598	
  3599		case 91: /* VSX instructions, XX4-form */
  3600			/* reg reg reg reg */
  3601			/* 3-register operand order: XA, XB, XC, XT */
  3602			o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
  3603	
  3604		case 92: /* X-form instructions, 3-operands */
  3605			if p.To.Type == obj.TYPE_CONST {
  3606				/* imm reg reg */
  3607				xf := int32(p.From.Reg)
  3608				if REG_F0 <= xf && xf <= REG_F31 {
  3609					/* operand order: FRA, FRB, BF */
  3610					bf := int(c.regoff(&p.To)) << 2
  3611					o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3612				} else {
  3613					/* operand order: RA, RB, L */
  3614					l := int(c.regoff(&p.To))
  3615					o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
  3616				}
  3617			} else if p.From3Type() == obj.TYPE_CONST {
  3618				/* reg reg imm */
  3619				/* operand order: RB, L, RA */
  3620				l := int(c.regoff(p.GetFrom3()))
  3621				o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
  3622			} else if p.To.Type == obj.TYPE_REG {
  3623				cr := int32(p.To.Reg)
  3624				if REG_CR0 <= cr && cr <= REG_CR7 {
  3625					/* cr reg reg */
  3626					/* operand order: RA, RB, BF */
  3627					bf := (int(p.To.Reg) & 7) << 2
  3628					o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
  3629				} else if p.From.Type == obj.TYPE_CONST {
  3630					/* reg imm */
  3631					/* operand order: L, RT */
  3632					l := int(c.regoff(&p.From))
  3633					o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
  3634				} else {
  3635					switch p.As {
  3636					case ACOPY, APASTECC:
  3637						o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
  3638					default:
  3639						/* reg reg reg */
  3640						/* operand order: RS, RB, RA */
  3641						o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3642					}
  3643				}
  3644			}
  3645	
  3646		case 93: /* X-form instructions, 2-operands */
  3647			if p.To.Type == obj.TYPE_CONST {
  3648				/* imm reg */
  3649				/* operand order: FRB, BF */
  3650				bf := int(c.regoff(&p.To)) << 2
  3651				o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
  3652			} else if p.Reg == 0 {
  3653				/* popcnt* r,r, X-form */
  3654				/* operand order: RS, RA */
  3655				o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
  3656			}
  3657	
  3658		case 94: /* Z23-form instructions, 4-operands */
  3659			/* reg reg reg imm */
  3660			/* operand order: RA, RB, CY, RT */
  3661			cy := int(c.regoff(p.GetFrom3()))
  3662			o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
  3663	
  3664		case 95: /* Retrieve TOC relative symbol */
  3665			/* This code is for AIX only */
  3666			v := c.vregoff(&p.From)
  3667			if v != 0 {
  3668				c.ctxt.Diag("invalid offset against TOC slot %v", p)
  3669			}
  3670	
  3671			inst := c.opload(p.As)
  3672			if c.opform(inst) != DS_FORM {
  3673				c.ctxt.Diag("invalid form for a TOC access in %v", p)
  3674			}
  3675	
  3676			o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
  3677			o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
  3678			rel := obj.Addrel(c.cursym)
  3679			rel.Off = int32(c.pc)
  3680			rel.Siz = 8
  3681			rel.Sym = p.From.Sym
  3682			rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
  3683		}
  3684	
  3685		out[0] = o1
  3686		out[1] = o2
  3687		out[2] = o3
  3688		out[3] = o4
  3689		out[4] = o5
  3690	}
  3691	
  3692	func (c *ctxt9) vregoff(a *obj.Addr) int64 {
  3693		c.instoffset = 0
  3694		if a != nil {
  3695			c.aclass(a)
  3696		}
  3697		return c.instoffset
  3698	}
  3699	
  3700	func (c *ctxt9) regoff(a *obj.Addr) int32 {
  3701		return int32(c.vregoff(a))
  3702	}
  3703	
  3704	func (c *ctxt9) oprrr(a obj.As) uint32 {
  3705		switch a {
  3706		case AADD:
  3707			return OPVCC(31, 266, 0, 0)
  3708		case AADDCC:
  3709			return OPVCC(31, 266, 0, 1)
  3710		case AADDV:
  3711			return OPVCC(31, 266, 1, 0)
  3712		case AADDVCC:
  3713			return OPVCC(31, 266, 1, 1)
  3714		case AADDC:
  3715			return OPVCC(31, 10, 0, 0)
  3716		case AADDCCC:
  3717			return OPVCC(31, 10, 0, 1)
  3718		case AADDCV:
  3719			return OPVCC(31, 10, 1, 0)
  3720		case AADDCVCC:
  3721			return OPVCC(31, 10, 1, 1)
  3722		case AADDE:
  3723			return OPVCC(31, 138, 0, 0)
  3724		case AADDECC:
  3725			return OPVCC(31, 138, 0, 1)
  3726		case AADDEV:
  3727			return OPVCC(31, 138, 1, 0)
  3728		case AADDEVCC:
  3729			return OPVCC(31, 138, 1, 1)
  3730		case AADDME:
  3731			return OPVCC(31, 234, 0, 0)
  3732		case AADDMECC:
  3733			return OPVCC(31, 234, 0, 1)
  3734		case AADDMEV:
  3735			return OPVCC(31, 234, 1, 0)
  3736		case AADDMEVCC:
  3737			return OPVCC(31, 234, 1, 1)
  3738		case AADDZE:
  3739			return OPVCC(31, 202, 0, 0)
  3740		case AADDZECC:
  3741			return OPVCC(31, 202, 0, 1)
  3742		case AADDZEV:
  3743			return OPVCC(31, 202, 1, 0)
  3744		case AADDZEVCC:
  3745			return OPVCC(31, 202, 1, 1)
  3746		case AADDEX:
  3747			return OPVCC(31, 170, 0, 0) /* addex - v3.0b */
  3748	
  3749		case AAND:
  3750			return OPVCC(31, 28, 0, 0)
  3751		case AANDCC:
  3752			return OPVCC(31, 28, 0, 1)
  3753		case AANDN:
  3754			return OPVCC(31, 60, 0, 0)
  3755		case AANDNCC:
  3756			return OPVCC(31, 60, 0, 1)
  3757	
  3758		case ACMP:
  3759			return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */
  3760		case ACMPU:
  3761			return OPVCC(31, 32, 0, 0) | 1<<21
  3762		case ACMPW:
  3763			return OPVCC(31, 0, 0, 0) /* L=0 */
  3764		case ACMPWU:
  3765			return OPVCC(31, 32, 0, 0)
  3766		case ACMPB:
  3767			return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */
  3768		case ACMPEQB:
  3769			return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  3770	
  3771		case ACNTLZW:
  3772			return OPVCC(31, 26, 0, 0)
  3773		case ACNTLZWCC:
  3774			return OPVCC(31, 26, 0, 1)
  3775		case ACNTLZD:
  3776			return OPVCC(31, 58, 0, 0)
  3777		case ACNTLZDCC:
  3778			return OPVCC(31, 58, 0, 1)
  3779	
  3780		case ACRAND:
  3781			return OPVCC(19, 257, 0, 0)
  3782		case ACRANDN:
  3783			return OPVCC(19, 129, 0, 0)
  3784		case ACREQV:
  3785			return OPVCC(19, 289, 0, 0)
  3786		case ACRNAND:
  3787			return OPVCC(19, 225, 0, 0)
  3788		case ACRNOR:
  3789			return OPVCC(19, 33, 0, 0)
  3790		case ACROR:
  3791			return OPVCC(19, 449, 0, 0)
  3792		case ACRORN:
  3793			return OPVCC(19, 417, 0, 0)
  3794		case ACRXOR:
  3795			return OPVCC(19, 193, 0, 0)
  3796	
  3797		case ADCBF:
  3798			return OPVCC(31, 86, 0, 0)
  3799		case ADCBI:
  3800			return OPVCC(31, 470, 0, 0)
  3801		case ADCBST:
  3802			return OPVCC(31, 54, 0, 0)
  3803		case ADCBT:
  3804			return OPVCC(31, 278, 0, 0)
  3805		case ADCBTST:
  3806			return OPVCC(31, 246, 0, 0)
  3807		case ADCBZ:
  3808			return OPVCC(31, 1014, 0, 0)
  3809	
  3810		case AREM, ADIVW:
  3811			return OPVCC(31, 491, 0, 0)
  3812	
  3813		case AREMCC, ADIVWCC:
  3814			return OPVCC(31, 491, 0, 1)
  3815	
  3816		case AREMV, ADIVWV:
  3817			return OPVCC(31, 491, 1, 0)
  3818	
  3819		case AREMVCC, ADIVWVCC:
  3820			return OPVCC(31, 491, 1, 1)
  3821	
  3822		case AREMU, ADIVWU:
  3823			return OPVCC(31, 459, 0, 0)
  3824	
  3825		case AREMUCC, ADIVWUCC:
  3826			return OPVCC(31, 459, 0, 1)
  3827	
  3828		case AREMUV, ADIVWUV:
  3829			return OPVCC(31, 459, 1, 0)
  3830	
  3831		case AREMUVCC, ADIVWUVCC:
  3832			return OPVCC(31, 459, 1, 1)
  3833	
  3834		case AREMD, ADIVD:
  3835			return OPVCC(31, 489, 0, 0)
  3836	
  3837		case AREMDCC, ADIVDCC:
  3838			return OPVCC(31, 489, 0, 1)
  3839	
  3840		case ADIVDE:
  3841			return OPVCC(31, 425, 0, 0)
  3842	
  3843		case ADIVDECC:
  3844			return OPVCC(31, 425, 0, 1)
  3845	
  3846		case ADIVDEU:
  3847			return OPVCC(31, 393, 0, 0)
  3848	
  3849		case ADIVDEUCC:
  3850			return OPVCC(31, 393, 0, 1)
  3851	
  3852		case AREMDV, ADIVDV:
  3853			return OPVCC(31, 489, 1, 0)
  3854	
  3855		case AREMDVCC, ADIVDVCC:
  3856			return OPVCC(31, 489, 1, 1)
  3857	
  3858		case AREMDU, ADIVDU:
  3859			return OPVCC(31, 457, 0, 0)
  3860	
  3861		case AREMDUCC, ADIVDUCC:
  3862			return OPVCC(31, 457, 0, 1)
  3863	
  3864		case AREMDUV, ADIVDUV:
  3865			return OPVCC(31, 457, 1, 0)
  3866	
  3867		case AREMDUVCC, ADIVDUVCC:
  3868			return OPVCC(31, 457, 1, 1)
  3869	
  3870		case AEIEIO:
  3871			return OPVCC(31, 854, 0, 0)
  3872	
  3873		case AEQV:
  3874			return OPVCC(31, 284, 0, 0)
  3875		case AEQVCC:
  3876			return OPVCC(31, 284, 0, 1)
  3877	
  3878		case AEXTSB:
  3879			return OPVCC(31, 954, 0, 0)
  3880		case AEXTSBCC:
  3881			return OPVCC(31, 954, 0, 1)
  3882		case AEXTSH:
  3883			return OPVCC(31, 922, 0, 0)
  3884		case AEXTSHCC:
  3885			return OPVCC(31, 922, 0, 1)
  3886		case AEXTSW:
  3887			return OPVCC(31, 986, 0, 0)
  3888		case AEXTSWCC:
  3889			return OPVCC(31, 986, 0, 1)
  3890	
  3891		case AFABS:
  3892			return OPVCC(63, 264, 0, 0)
  3893		case AFABSCC:
  3894			return OPVCC(63, 264, 0, 1)
  3895		case AFADD:
  3896			return OPVCC(63, 21, 0, 0)
  3897		case AFADDCC:
  3898			return OPVCC(63, 21, 0, 1)
  3899		case AFADDS:
  3900			return OPVCC(59, 21, 0, 0)
  3901		case AFADDSCC:
  3902			return OPVCC(59, 21, 0, 1)
  3903		case AFCMPO:
  3904			return OPVCC(63, 32, 0, 0)
  3905		case AFCMPU:
  3906			return OPVCC(63, 0, 0, 0)
  3907		case AFCFID:
  3908			return OPVCC(63, 846, 0, 0)
  3909		case AFCFIDCC:
  3910			return OPVCC(63, 846, 0, 1)
  3911		case AFCFIDU:
  3912			return OPVCC(63, 974, 0, 0)
  3913		case AFCFIDUCC:
  3914			return OPVCC(63, 974, 0, 1)
  3915		case AFCFIDS:
  3916			return OPVCC(59, 846, 0, 0)
  3917		case AFCFIDSCC:
  3918			return OPVCC(59, 846, 0, 1)
  3919		case AFCTIW:
  3920			return OPVCC(63, 14, 0, 0)
  3921		case AFCTIWCC:
  3922			return OPVCC(63, 14, 0, 1)
  3923		case AFCTIWZ:
  3924			return OPVCC(63, 15, 0, 0)
  3925		case AFCTIWZCC:
  3926			return OPVCC(63, 15, 0, 1)
  3927		case AFCTID:
  3928			return OPVCC(63, 814, 0, 0)
  3929		case AFCTIDCC:
  3930			return OPVCC(63, 814, 0, 1)
  3931		case AFCTIDZ:
  3932			return OPVCC(63, 815, 0, 0)
  3933		case AFCTIDZCC:
  3934			return OPVCC(63, 815, 0, 1)
  3935		case AFDIV:
  3936			return OPVCC(63, 18, 0, 0)
  3937		case AFDIVCC:
  3938			return OPVCC(63, 18, 0, 1)
  3939		case AFDIVS:
  3940			return OPVCC(59, 18, 0, 0)
  3941		case AFDIVSCC:
  3942			return OPVCC(59, 18, 0, 1)
  3943		case AFMADD:
  3944			return OPVCC(63, 29, 0, 0)
  3945		case AFMADDCC:
  3946			return OPVCC(63, 29, 0, 1)
  3947		case AFMADDS:
  3948			return OPVCC(59, 29, 0, 0)
  3949		case AFMADDSCC:
  3950			return OPVCC(59, 29, 0, 1)
  3951	
  3952		case AFMOVS, AFMOVD:
  3953			return OPVCC(63, 72, 0, 0) /* load */
  3954		case AFMOVDCC:
  3955			return OPVCC(63, 72, 0, 1)
  3956		case AFMSUB:
  3957			return OPVCC(63, 28, 0, 0)
  3958		case AFMSUBCC:
  3959			return OPVCC(63, 28, 0, 1)
  3960		case AFMSUBS:
  3961			return OPVCC(59, 28, 0, 0)
  3962		case AFMSUBSCC:
  3963			return OPVCC(59, 28, 0, 1)
  3964		case AFMUL:
  3965			return OPVCC(63, 25, 0, 0)
  3966		case AFMULCC:
  3967			return OPVCC(63, 25, 0, 1)
  3968		case AFMULS:
  3969			return OPVCC(59, 25, 0, 0)
  3970		case AFMULSCC:
  3971			return OPVCC(59, 25, 0, 1)
  3972		case AFNABS:
  3973			return OPVCC(63, 136, 0, 0)
  3974		case AFNABSCC:
  3975			return OPVCC(63, 136, 0, 1)
  3976		case AFNEG:
  3977			return OPVCC(63, 40, 0, 0)
  3978		case AFNEGCC:
  3979			return OPVCC(63, 40, 0, 1)
  3980		case AFNMADD:
  3981			return OPVCC(63, 31, 0, 0)
  3982		case AFNMADDCC:
  3983			return OPVCC(63, 31, 0, 1)
  3984		case AFNMADDS:
  3985			return OPVCC(59, 31, 0, 0)
  3986		case AFNMADDSCC:
  3987			return OPVCC(59, 31, 0, 1)
  3988		case AFNMSUB:
  3989			return OPVCC(63, 30, 0, 0)
  3990		case AFNMSUBCC:
  3991			return OPVCC(63, 30, 0, 1)
  3992		case AFNMSUBS:
  3993			return OPVCC(59, 30, 0, 0)
  3994		case AFNMSUBSCC:
  3995			return OPVCC(59, 30, 0, 1)
  3996		case AFCPSGN:
  3997			return OPVCC(63, 8, 0, 0)
  3998		case AFCPSGNCC:
  3999			return OPVCC(63, 8, 0, 1)
  4000		case AFRES:
  4001			return OPVCC(59, 24, 0, 0)
  4002		case AFRESCC:
  4003			return OPVCC(59, 24, 0, 1)
  4004		case AFRIM:
  4005			return OPVCC(63, 488, 0, 0)
  4006		case AFRIMCC:
  4007			return OPVCC(63, 488, 0, 1)
  4008		case AFRIP:
  4009			return OPVCC(63, 456, 0, 0)
  4010		case AFRIPCC:
  4011			return OPVCC(63, 456, 0, 1)
  4012		case AFRIZ:
  4013			return OPVCC(63, 424, 0, 0)
  4014		case AFRIZCC:
  4015			return OPVCC(63, 424, 0, 1)
  4016		case AFRIN:
  4017			return OPVCC(63, 392, 0, 0)
  4018		case AFRINCC:
  4019			return OPVCC(63, 392, 0, 1)
  4020		case AFRSP:
  4021			return OPVCC(63, 12, 0, 0)
  4022		case AFRSPCC:
  4023			return OPVCC(63, 12, 0, 1)
  4024		case AFRSQRTE:
  4025			return OPVCC(63, 26, 0, 0)
  4026		case AFRSQRTECC:
  4027			return OPVCC(63, 26, 0, 1)
  4028		case AFSEL:
  4029			return OPVCC(63, 23, 0, 0)
  4030		case AFSELCC:
  4031			return OPVCC(63, 23, 0, 1)
  4032		case AFSQRT:
  4033			return OPVCC(63, 22, 0, 0)
  4034		case AFSQRTCC:
  4035			return OPVCC(63, 22, 0, 1)
  4036		case AFSQRTS:
  4037			return OPVCC(59, 22, 0, 0)
  4038		case AFSQRTSCC:
  4039			return OPVCC(59, 22, 0, 1)
  4040		case AFSUB:
  4041			return OPVCC(63, 20, 0, 0)
  4042		case AFSUBCC:
  4043			return OPVCC(63, 20, 0, 1)
  4044		case AFSUBS:
  4045			return OPVCC(59, 20, 0, 0)
  4046		case AFSUBSCC:
  4047			return OPVCC(59, 20, 0, 1)
  4048	
  4049		case AICBI:
  4050			return OPVCC(31, 982, 0, 0)
  4051		case AISYNC:
  4052			return OPVCC(19, 150, 0, 0)
  4053	
  4054		case AMTFSB0:
  4055			return OPVCC(63, 70, 0, 0)
  4056		case AMTFSB0CC:
  4057			return OPVCC(63, 70, 0, 1)
  4058		case AMTFSB1:
  4059			return OPVCC(63, 38, 0, 0)
  4060		case AMTFSB1CC:
  4061			return OPVCC(63, 38, 0, 1)
  4062	
  4063		case AMULHW:
  4064			return OPVCC(31, 75, 0, 0)
  4065		case AMULHWCC:
  4066			return OPVCC(31, 75, 0, 1)
  4067		case AMULHWU:
  4068			return OPVCC(31, 11, 0, 0)
  4069		case AMULHWUCC:
  4070			return OPVCC(31, 11, 0, 1)
  4071		case AMULLW:
  4072			return OPVCC(31, 235, 0, 0)
  4073		case AMULLWCC:
  4074			return OPVCC(31, 235, 0, 1)
  4075		case AMULLWV:
  4076			return OPVCC(31, 235, 1, 0)
  4077		case AMULLWVCC:
  4078			return OPVCC(31, 235, 1, 1)
  4079	
  4080		case AMULHD:
  4081			return OPVCC(31, 73, 0, 0)
  4082		case AMULHDCC:
  4083			return OPVCC(31, 73, 0, 1)
  4084		case AMULHDU:
  4085			return OPVCC(31, 9, 0, 0)
  4086		case AMULHDUCC:
  4087			return OPVCC(31, 9, 0, 1)
  4088		case AMULLD:
  4089			return OPVCC(31, 233, 0, 0)
  4090		case AMULLDCC:
  4091			return OPVCC(31, 233, 0, 1)
  4092		case AMULLDV:
  4093			return OPVCC(31, 233, 1, 0)
  4094		case AMULLDVCC:
  4095			return OPVCC(31, 233, 1, 1)
  4096	
  4097		case ANAND:
  4098			return OPVCC(31, 476, 0, 0)
  4099		case ANANDCC:
  4100			return OPVCC(31, 476, 0, 1)
  4101		case ANEG:
  4102			return OPVCC(31, 104, 0, 0)
  4103		case ANEGCC:
  4104			return OPVCC(31, 104, 0, 1)
  4105		case ANEGV:
  4106			return OPVCC(31, 104, 1, 0)
  4107		case ANEGVCC:
  4108			return OPVCC(31, 104, 1, 1)
  4109		case ANOR:
  4110			return OPVCC(31, 124, 0, 0)
  4111		case ANORCC:
  4112			return OPVCC(31, 124, 0, 1)
  4113		case AOR:
  4114			return OPVCC(31, 444, 0, 0)
  4115		case AORCC:
  4116			return OPVCC(31, 444, 0, 1)
  4117		case AORN:
  4118			return OPVCC(31, 412, 0, 0)
  4119		case AORNCC:
  4120			return OPVCC(31, 412, 0, 1)
  4121	
  4122		case APOPCNTD:
  4123			return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */
  4124		case APOPCNTW:
  4125			return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */
  4126		case APOPCNTB:
  4127			return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */
  4128		case ACNTTZW:
  4129			return OPVCC(31, 538, 0, 0) /* cnttzw - v3.00 */
  4130		case ACNTTZWCC:
  4131			return OPVCC(31, 538, 0, 1) /* cnttzw. - v3.00 */
  4132		case ACNTTZD:
  4133			return OPVCC(31, 570, 0, 0) /* cnttzd - v3.00 */
  4134		case ACNTTZDCC:
  4135			return OPVCC(31, 570, 0, 1) /* cnttzd. - v3.00 */
  4136	
  4137		case ARFI:
  4138			return OPVCC(19, 50, 0, 0)
  4139		case ARFCI:
  4140			return OPVCC(19, 51, 0, 0)
  4141		case ARFID:
  4142			return OPVCC(19, 18, 0, 0)
  4143		case AHRFID:
  4144			return OPVCC(19, 274, 0, 0)
  4145	
  4146		case ARLWMI:
  4147			return OPVCC(20, 0, 0, 0)
  4148		case ARLWMICC:
  4149			return OPVCC(20, 0, 0, 1)
  4150		case ARLWNM:
  4151			return OPVCC(23, 0, 0, 0)
  4152		case ARLWNMCC:
  4153			return OPVCC(23, 0, 0, 1)
  4154	
  4155		case ARLDCL:
  4156			return OPVCC(30, 8, 0, 0)
  4157		case ARLDCR:
  4158			return OPVCC(30, 9, 0, 0)
  4159	
  4160		case ARLDICL:
  4161			return OPVCC(30, 0, 0, 0)
  4162		case ARLDICLCC:
  4163			return OPVCC(30, 0, 0, 1)
  4164		case ARLDICR:
  4165			return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr
  4166		case ARLDICRCC:
  4167			return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr.
  4168	
  4169		case ASYSCALL:
  4170			return OPVCC(17, 1, 0, 0)
  4171	
  4172		case ASLW:
  4173			return OPVCC(31, 24, 0, 0)
  4174		case ASLWCC:
  4175			return OPVCC(31, 24, 0, 1)
  4176		case ASLD:
  4177			return OPVCC(31, 27, 0, 0)
  4178		case ASLDCC:
  4179			return OPVCC(31, 27, 0, 1)
  4180	
  4181		case ASRAW:
  4182			return OPVCC(31, 792, 0, 0)
  4183		case ASRAWCC:
  4184			return OPVCC(31, 792, 0, 1)
  4185		case ASRAD:
  4186			return OPVCC(31, 794, 0, 0)
  4187		case ASRADCC:
  4188			return OPVCC(31, 794, 0, 1)
  4189	
  4190		case ASRW:
  4191			return OPVCC(31, 536, 0, 0)
  4192		case ASRWCC:
  4193			return OPVCC(31, 536, 0, 1)
  4194		case ASRD:
  4195			return OPVCC(31, 539, 0, 0)
  4196		case ASRDCC:
  4197			return OPVCC(31, 539, 0, 1)
  4198	
  4199		case ASUB:
  4200			return OPVCC(31, 40, 0, 0)
  4201		case ASUBCC:
  4202			return OPVCC(31, 40, 0, 1)
  4203		case ASUBV:
  4204			return OPVCC(31, 40, 1, 0)
  4205		case ASUBVCC:
  4206			return OPVCC(31, 40, 1, 1)
  4207		case ASUBC:
  4208			return OPVCC(31, 8, 0, 0)
  4209		case ASUBCCC:
  4210			return OPVCC(31, 8, 0, 1)
  4211		case ASUBCV:
  4212			return OPVCC(31, 8, 1, 0)
  4213		case ASUBCVCC:
  4214			return OPVCC(31, 8, 1, 1)
  4215		case ASUBE:
  4216			return OPVCC(31, 136, 0, 0)
  4217		case ASUBECC:
  4218			return OPVCC(31, 136, 0, 1)
  4219		case ASUBEV:
  4220			return OPVCC(31, 136, 1, 0)
  4221		case ASUBEVCC:
  4222			return OPVCC(31, 136, 1, 1)
  4223		case ASUBME:
  4224			return OPVCC(31, 232, 0, 0)
  4225		case ASUBMECC:
  4226			return OPVCC(31, 232, 0, 1)
  4227		case ASUBMEV:
  4228			return OPVCC(31, 232, 1, 0)
  4229		case ASUBMEVCC:
  4230			return OPVCC(31, 232, 1, 1)
  4231		case ASUBZE:
  4232			return OPVCC(31, 200, 0, 0)
  4233		case ASUBZECC:
  4234			return OPVCC(31, 200, 0, 1)
  4235		case ASUBZEV:
  4236			return OPVCC(31, 200, 1, 0)
  4237		case ASUBZEVCC:
  4238			return OPVCC(31, 200, 1, 1)
  4239	
  4240		case ASYNC:
  4241			return OPVCC(31, 598, 0, 0)
  4242		case ALWSYNC:
  4243			return OPVCC(31, 598, 0, 0) | 1<<21
  4244	
  4245		case APTESYNC:
  4246			return OPVCC(31, 598, 0, 0) | 2<<21
  4247	
  4248		case ATLBIE:
  4249			return OPVCC(31, 306, 0, 0)
  4250		case ATLBIEL:
  4251			return OPVCC(31, 274, 0, 0)
  4252		case ATLBSYNC:
  4253			return OPVCC(31, 566, 0, 0)
  4254		case ASLBIA:
  4255			return OPVCC(31, 498, 0, 0)
  4256		case ASLBIE:
  4257			return OPVCC(31, 434, 0, 0)
  4258		case ASLBMFEE:
  4259			return OPVCC(31, 915, 0, 0)
  4260		case ASLBMFEV:
  4261			return OPVCC(31, 851, 0, 0)
  4262		case ASLBMTE:
  4263			return OPVCC(31, 402, 0, 0)
  4264	
  4265		case ATW:
  4266			return OPVCC(31, 4, 0, 0)
  4267		case ATD:
  4268			return OPVCC(31, 68, 0, 0)
  4269	
  4270		/* Vector (VMX/Altivec) instructions */
  4271		/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4272		/* are enabled starting at POWER6 (ISA 2.05). */
  4273		case AVAND:
  4274			return OPVX(4, 1028, 0, 0) /* vand - v2.03 */
  4275		case AVANDC:
  4276			return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */
  4277		case AVNAND:
  4278			return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */
  4279	
  4280		case AVOR:
  4281			return OPVX(4, 1156, 0, 0) /* vor - v2.03 */
  4282		case AVORC:
  4283			return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */
  4284		case AVNOR:
  4285			return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */
  4286		case AVXOR:
  4287			return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */
  4288		case AVEQV:
  4289			return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */
  4290	
  4291		case AVADDUBM:
  4292			return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */
  4293		case AVADDUHM:
  4294			return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */
  4295		case AVADDUWM:
  4296			return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */
  4297		case AVADDUDM:
  4298			return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */
  4299		case AVADDUQM:
  4300			return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */
  4301	
  4302		case AVADDCUQ:
  4303			return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */
  4304		case AVADDCUW:
  4305			return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */
  4306	
  4307		case AVADDUBS:
  4308			return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */
  4309		case AVADDUHS:
  4310			return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */
  4311		case AVADDUWS:
  4312			return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */
  4313	
  4314		case AVADDSBS:
  4315			return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */
  4316		case AVADDSHS:
  4317			return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */
  4318		case AVADDSWS:
  4319			return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */
  4320	
  4321		case AVADDEUQM:
  4322			return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */
  4323		case AVADDECUQ:
  4324			return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */
  4325	
  4326		case AVMULESB:
  4327			return OPVX(4, 776, 0, 0) /* vmulesb - v2.03 */
  4328		case AVMULOSB:
  4329			return OPVX(4, 264, 0, 0) /* vmulosb - v2.03 */
  4330		case AVMULEUB:
  4331			return OPVX(4, 520, 0, 0) /* vmuleub - v2.03 */
  4332		case AVMULOUB:
  4333			return OPVX(4, 8, 0, 0) /* vmuloub - v2.03 */
  4334		case AVMULESH:
  4335			return OPVX(4, 840, 0, 0) /* vmulesh - v2.03 */
  4336		case AVMULOSH:
  4337			return OPVX(4, 328, 0, 0) /* vmulosh - v2.03 */
  4338		case AVMULEUH:
  4339			return OPVX(4, 584, 0, 0) /* vmuleuh - v2.03 */
  4340		case AVMULOUH:
  4341			return OPVX(4, 72, 0, 0) /* vmulouh - v2.03 */
  4342		case AVMULESW:
  4343			return OPVX(4, 904, 0, 0) /* vmulesw - v2.07 */
  4344		case AVMULOSW:
  4345			return OPVX(4, 392, 0, 0) /* vmulosw - v2.07 */
  4346		case AVMULEUW:
  4347			return OPVX(4, 648, 0, 0) /* vmuleuw - v2.07 */
  4348		case AVMULOUW:
  4349			return OPVX(4, 136, 0, 0) /* vmulouw - v2.07 */
  4350		case AVMULUWM:
  4351			return OPVX(4, 137, 0, 0) /* vmuluwm - v2.07 */
  4352	
  4353		case AVPMSUMB:
  4354			return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */
  4355		case AVPMSUMH:
  4356			return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */
  4357		case AVPMSUMW:
  4358			return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */
  4359		case AVPMSUMD:
  4360			return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */
  4361	
  4362		case AVMSUMUDM:
  4363			return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */
  4364	
  4365		case AVSUBUBM:
  4366			return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */
  4367		case AVSUBUHM:
  4368			return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */
  4369		case AVSUBUWM:
  4370			return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */
  4371		case AVSUBUDM:
  4372			return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */
  4373		case AVSUBUQM:
  4374			return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */
  4375	
  4376		case AVSUBCUQ:
  4377			return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */
  4378		case AVSUBCUW:
  4379			return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */
  4380	
  4381		case AVSUBUBS:
  4382			return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */
  4383		case AVSUBUHS:
  4384			return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */
  4385		case AVSUBUWS:
  4386			return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */
  4387	
  4388		case AVSUBSBS:
  4389			return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */
  4390		case AVSUBSHS:
  4391			return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */
  4392		case AVSUBSWS:
  4393			return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */
  4394	
  4395		case AVSUBEUQM:
  4396			return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */
  4397		case AVSUBECUQ:
  4398			return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */
  4399	
  4400		case AVRLB:
  4401			return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */
  4402		case AVRLH:
  4403			return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */
  4404		case AVRLW:
  4405			return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */
  4406		case AVRLD:
  4407			return OPVX(4, 196, 0, 0) /* vrld - v2.07 */
  4408	
  4409		case AVSLB:
  4410			return OPVX(4, 260, 0, 0) /* vslh - v2.03 */
  4411		case AVSLH:
  4412			return OPVX(4, 324, 0, 0) /* vslh - v2.03 */
  4413		case AVSLW:
  4414			return OPVX(4, 388, 0, 0) /* vslw - v2.03 */
  4415		case AVSL:
  4416			return OPVX(4, 452, 0, 0) /* vsl - v2.03 */
  4417		case AVSLO:
  4418			return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */
  4419		case AVSRB:
  4420			return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */
  4421		case AVSRH:
  4422			return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */
  4423		case AVSRW:
  4424			return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */
  4425		case AVSR:
  4426			return OPVX(4, 708, 0, 0) /* vsr - v2.03 */
  4427		case AVSRO:
  4428			return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */
  4429		case AVSLD:
  4430			return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */
  4431		case AVSRD:
  4432			return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */
  4433	
  4434		case AVSRAB:
  4435			return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */
  4436		case AVSRAH:
  4437			return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */
  4438		case AVSRAW:
  4439			return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */
  4440		case AVSRAD:
  4441			return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */
  4442	
  4443		case AVBPERMQ:
  4444			return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */
  4445		case AVBPERMD:
  4446			return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */
  4447	
  4448		case AVCLZB:
  4449			return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */
  4450		case AVCLZH:
  4451			return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */
  4452		case AVCLZW:
  4453			return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */
  4454		case AVCLZD:
  4455			return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */
  4456	
  4457		case AVPOPCNTB:
  4458			return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */
  4459		case AVPOPCNTH:
  4460			return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */
  4461		case AVPOPCNTW:
  4462			return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */
  4463		case AVPOPCNTD:
  4464			return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */
  4465	
  4466		case AVCMPEQUB:
  4467			return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */
  4468		case AVCMPEQUBCC:
  4469			return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */
  4470		case AVCMPEQUH:
  4471			return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */
  4472		case AVCMPEQUHCC:
  4473			return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */
  4474		case AVCMPEQUW:
  4475			return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */
  4476		case AVCMPEQUWCC:
  4477			return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */
  4478		case AVCMPEQUD:
  4479			return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */
  4480		case AVCMPEQUDCC:
  4481			return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */
  4482	
  4483		case AVCMPGTUB:
  4484			return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */
  4485		case AVCMPGTUBCC:
  4486			return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */
  4487		case AVCMPGTUH:
  4488			return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */
  4489		case AVCMPGTUHCC:
  4490			return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */
  4491		case AVCMPGTUW:
  4492			return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */
  4493		case AVCMPGTUWCC:
  4494			return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */
  4495		case AVCMPGTUD:
  4496			return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */
  4497		case AVCMPGTUDCC:
  4498			return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */
  4499		case AVCMPGTSB:
  4500			return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */
  4501		case AVCMPGTSBCC:
  4502			return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */
  4503		case AVCMPGTSH:
  4504			return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */
  4505		case AVCMPGTSHCC:
  4506			return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */
  4507		case AVCMPGTSW:
  4508			return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */
  4509		case AVCMPGTSWCC:
  4510			return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */
  4511		case AVCMPGTSD:
  4512			return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */
  4513		case AVCMPGTSDCC:
  4514			return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */
  4515	
  4516		case AVCMPNEZB:
  4517			return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */
  4518		case AVCMPNEZBCC:
  4519			return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */
  4520	
  4521		case AVPERM:
  4522			return OPVX(4, 43, 0, 0) /* vperm - v2.03 */
  4523		case AVPERMXOR:
  4524			return OPVX(4, 45, 0, 0) /* vpermxor - v2.03 */
  4525	
  4526		case AVSEL:
  4527			return OPVX(4, 42, 0, 0) /* vsel - v2.03 */
  4528	
  4529		case AVCIPHER:
  4530			return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */
  4531		case AVCIPHERLAST:
  4532			return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */
  4533		case AVNCIPHER:
  4534			return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */
  4535		case AVNCIPHERLAST:
  4536			return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */
  4537		case AVSBOX:
  4538			return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */
  4539		/* End of vector instructions */
  4540	
  4541		/* Vector scalar (VSX) instructions */
  4542		/* ISA 2.06 enables these for POWER7. */
  4543		case AMFVSRD, AMFVRD, AMFFPRD:
  4544			return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */
  4545		case AMFVSRWZ:
  4546			return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */
  4547		case AMFVSRLD:
  4548			return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */
  4549	
  4550		case AMTVSRD, AMTFPRD, AMTVRD:
  4551			return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */
  4552		case AMTVSRWA:
  4553			return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */
  4554		case AMTVSRWZ:
  4555			return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */
  4556		case AMTVSRDD:
  4557			return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */
  4558		case AMTVSRWS:
  4559			return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */
  4560	
  4561		case AXXLANDQ:
  4562			return OPVXX3(60, 130, 0) /* xxland - v2.06 */
  4563		case AXXLANDC:
  4564			return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */
  4565		case AXXLEQV:
  4566			return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */
  4567		case AXXLNAND:
  4568			return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */
  4569	
  4570		case AXXLORC:
  4571			return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */
  4572		case AXXLNOR:
  4573			return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */
  4574		case AXXLORQ:
  4575			return OPVXX3(60, 146, 0) /* xxlor - v2.06 */
  4576		case AXXLXOR:
  4577			return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */
  4578	
  4579		case AXXSEL:
  4580			return OPVXX4(60, 3, 0) /* xxsel - v2.06 */
  4581	
  4582		case AXXMRGHW:
  4583			return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */
  4584		case AXXMRGLW:
  4585			return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */
  4586	
  4587		case AXXSPLTW:
  4588			return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */
  4589	
  4590		case AXXPERMDI:
  4591			return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */
  4592	
  4593		case AXXSLDWI:
  4594			return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */
  4595	
  4596		case AXSCVDPSP:
  4597			return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */
  4598		case AXSCVSPDP:
  4599			return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */
  4600		case AXSCVDPSPN:
  4601			return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */
  4602		case AXSCVSPDPN:
  4603			return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */
  4604	
  4605		case AXVCVDPSP:
  4606			return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */
  4607		case AXVCVSPDP:
  4608			return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */
  4609	
  4610		case AXSCVDPSXDS:
  4611			return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */
  4612		case AXSCVDPSXWS:
  4613			return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */
  4614		case AXSCVDPUXDS:
  4615			return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */
  4616		case AXSCVDPUXWS:
  4617			return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */
  4618	
  4619		case AXSCVSXDDP:
  4620			return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */
  4621		case AXSCVUXDDP:
  4622			return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */
  4623		case AXSCVSXDSP:
  4624			return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */
  4625		case AXSCVUXDSP:
  4626			return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */
  4627	
  4628		case AXVCVDPSXDS:
  4629			return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */
  4630		case AXVCVDPSXWS:
  4631			return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */
  4632		case AXVCVDPUXDS:
  4633			return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */
  4634		case AXVCVDPUXWS:
  4635			return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */
  4636		case AXVCVSPSXDS:
  4637			return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */
  4638		case AXVCVSPSXWS:
  4639			return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */
  4640		case AXVCVSPUXDS:
  4641			return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */
  4642		case AXVCVSPUXWS:
  4643			return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */
  4644	
  4645		case AXVCVSXDDP:
  4646			return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */
  4647		case AXVCVSXWDP:
  4648			return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */
  4649		case AXVCVUXDDP:
  4650			return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */
  4651		case AXVCVUXWDP:
  4652			return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */
  4653		case AXVCVSXDSP:
  4654			return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */
  4655		case AXVCVSXWSP:
  4656			return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */
  4657		case AXVCVUXDSP:
  4658			return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */
  4659		case AXVCVUXWSP:
  4660			return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */
  4661		/* End of VSX instructions */
  4662	
  4663		case AMADDHD:
  4664			return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */
  4665		case AMADDHDU:
  4666			return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */
  4667		case AMADDLD:
  4668			return OPVX(4, 51, 0, 0) /* maddld - v3.00 */
  4669	
  4670		case AXOR:
  4671			return OPVCC(31, 316, 0, 0)
  4672		case AXORCC:
  4673			return OPVCC(31, 316, 0, 1)
  4674		}
  4675	
  4676		c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
  4677		return 0
  4678	}
  4679	
  4680	func (c *ctxt9) opirrr(a obj.As) uint32 {
  4681		switch a {
  4682		/* Vector (VMX/Altivec) instructions */
  4683		/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4684		/* are enabled starting at POWER6 (ISA 2.05). */
  4685		case AVSLDOI:
  4686			return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */
  4687		}
  4688	
  4689		c.ctxt.Diag("bad i/r/r/r opcode %v", a)
  4690		return 0
  4691	}
  4692	
  4693	func (c *ctxt9) opiirr(a obj.As) uint32 {
  4694		switch a {
  4695		/* Vector (VMX/Altivec) instructions */
  4696		/* ISA 2.07 enables these for POWER8 and beyond. */
  4697		case AVSHASIGMAW:
  4698			return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */
  4699		case AVSHASIGMAD:
  4700			return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */
  4701		}
  4702	
  4703		c.ctxt.Diag("bad i/i/r/r opcode %v", a)
  4704		return 0
  4705	}
  4706	
  4707	func (c *ctxt9) opirr(a obj.As) uint32 {
  4708		switch a {
  4709		case AADD:
  4710			return OPVCC(14, 0, 0, 0)
  4711		case AADDC:
  4712			return OPVCC(12, 0, 0, 0)
  4713		case AADDCCC:
  4714			return OPVCC(13, 0, 0, 0)
  4715		case AADDIS:
  4716			return OPVCC(15, 0, 0, 0) /* ADDIS */
  4717	
  4718		case AANDCC:
  4719			return OPVCC(28, 0, 0, 0)
  4720		case AANDISCC:
  4721			return OPVCC(29, 0, 0, 0) /* ANDIS. */
  4722	
  4723		case ABR:
  4724			return OPVCC(18, 0, 0, 0)
  4725		case ABL:
  4726			return OPVCC(18, 0, 0, 0) | 1
  4727		case obj.ADUFFZERO:
  4728			return OPVCC(18, 0, 0, 0) | 1
  4729		case obj.ADUFFCOPY:
  4730			return OPVCC(18, 0, 0, 0) | 1
  4731		case ABC:
  4732			return OPVCC(16, 0, 0, 0)
  4733		case ABCL:
  4734			return OPVCC(16, 0, 0, 0) | 1
  4735	
  4736		case ABEQ:
  4737			return AOP_RRR(16<<26, 12, 2, 0)
  4738		case ABGE:
  4739			return AOP_RRR(16<<26, 4, 0, 0)
  4740		case ABGT:
  4741			return AOP_RRR(16<<26, 12, 1, 0)
  4742		case ABLE:
  4743			return AOP_RRR(16<<26, 4, 1, 0)
  4744		case ABLT:
  4745			return AOP_RRR(16<<26, 12, 0, 0)
  4746		case ABNE:
  4747			return AOP_RRR(16<<26, 4, 2, 0)
  4748		case ABVC:
  4749			return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear
  4750		case ABVS:
  4751			return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set
  4752	
  4753		case ACMP:
  4754			return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */
  4755		case ACMPU:
  4756			return OPVCC(10, 0, 0, 0) | 1<<21
  4757		case ACMPW:
  4758			return OPVCC(11, 0, 0, 0) /* L=0 */
  4759		case ACMPWU:
  4760			return OPVCC(10, 0, 0, 0)
  4761		case ACMPEQB:
  4762			return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */
  4763	
  4764		case ALSW:
  4765			return OPVCC(31, 597, 0, 0)
  4766	
  4767		case ACOPY:
  4768			return OPVCC(31, 774, 0, 0) /* copy - v3.00 */
  4769		case APASTECC:
  4770			return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */
  4771		case ADARN:
  4772			return OPVCC(31, 755, 0, 0) /* darn - v3.00 */
  4773	
  4774		case AMULLW:
  4775			return OPVCC(7, 0, 0, 0)
  4776	
  4777		case AOR:
  4778			return OPVCC(24, 0, 0, 0)
  4779		case AORIS:
  4780			return OPVCC(25, 0, 0, 0) /* ORIS */
  4781	
  4782		case ARLWMI:
  4783			return OPVCC(20, 0, 0, 0) /* rlwimi */
  4784		case ARLWMICC:
  4785			return OPVCC(20, 0, 0, 1)
  4786		case ARLDMI:
  4787			return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */
  4788		case ARLDMICC:
  4789			return OPVCC(30, 0, 0, 1) | 3<<2
  4790		case ARLDIMI:
  4791			return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */
  4792		case ARLDIMICC:
  4793			return OPVCC(30, 0, 0, 1) | 3<<2
  4794		case ARLWNM:
  4795			return OPVCC(21, 0, 0, 0) /* rlwinm */
  4796		case ARLWNMCC:
  4797			return OPVCC(21, 0, 0, 1)
  4798	
  4799		case ARLDCL:
  4800			return OPVCC(30, 0, 0, 0) /* rldicl */
  4801		case ARLDCLCC:
  4802			return OPVCC(30, 0, 0, 1)
  4803		case ARLDCR:
  4804			return OPVCC(30, 1, 0, 0) /* rldicr */
  4805		case ARLDCRCC:
  4806			return OPVCC(30, 1, 0, 1)
  4807		case ARLDC:
  4808			return OPVCC(30, 0, 0, 0) | 2<<2
  4809		case ARLDCCC:
  4810			return OPVCC(30, 0, 0, 1) | 2<<2
  4811	
  4812		case ASRAW:
  4813			return OPVCC(31, 824, 0, 0)
  4814		case ASRAWCC:
  4815			return OPVCC(31, 824, 0, 1)
  4816		case ASRAD:
  4817			return OPVCC(31, (413 << 1), 0, 0)
  4818		case ASRADCC:
  4819			return OPVCC(31, (413 << 1), 0, 1)
  4820	
  4821		case ASTSW:
  4822			return OPVCC(31, 725, 0, 0)
  4823	
  4824		case ASUBC:
  4825			return OPVCC(8, 0, 0, 0)
  4826	
  4827		case ATW:
  4828			return OPVCC(3, 0, 0, 0)
  4829		case ATD:
  4830			return OPVCC(2, 0, 0, 0)
  4831	
  4832		/* Vector (VMX/Altivec) instructions */
  4833		/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4834		/* are enabled starting at POWER6 (ISA 2.05). */
  4835		case AVSPLTB:
  4836			return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */
  4837		case AVSPLTH:
  4838			return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */
  4839		case AVSPLTW:
  4840			return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */
  4841	
  4842		case AVSPLTISB:
  4843			return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */
  4844		case AVSPLTISH:
  4845			return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */
  4846		case AVSPLTISW:
  4847			return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */
  4848		/* End of vector instructions */
  4849	
  4850		case AFTDIV:
  4851			return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */
  4852		case AFTSQRT:
  4853			return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */
  4854	
  4855		case AXOR:
  4856			return OPVCC(26, 0, 0, 0) /* XORIL */
  4857		case AXORIS:
  4858			return OPVCC(27, 0, 0, 0) /* XORIS */
  4859		}
  4860	
  4861		c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
  4862		return 0
  4863	}
  4864	
  4865	/*
  4866	 * load o(a),d
  4867	 */
  4868	func (c *ctxt9) opload(a obj.As) uint32 {
  4869		switch a {
  4870		case AMOVD:
  4871			return OPVCC(58, 0, 0, 0) /* ld */
  4872		case AMOVDU:
  4873			return OPVCC(58, 0, 0, 1) /* ldu */
  4874		case AMOVWZ:
  4875			return OPVCC(32, 0, 0, 0) /* lwz */
  4876		case AMOVWZU:
  4877			return OPVCC(33, 0, 0, 0) /* lwzu */
  4878		case AMOVW:
  4879			return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */
  4880	
  4881			/* no AMOVWU */
  4882		case AMOVB, AMOVBZ:
  4883			return OPVCC(34, 0, 0, 0)
  4884			/* load */
  4885	
  4886		case AMOVBU, AMOVBZU:
  4887			return OPVCC(35, 0, 0, 0)
  4888		case AFMOVD:
  4889			return OPVCC(50, 0, 0, 0)
  4890		case AFMOVDU:
  4891			return OPVCC(51, 0, 0, 0)
  4892		case AFMOVS:
  4893			return OPVCC(48, 0, 0, 0)
  4894		case AFMOVSU:
  4895			return OPVCC(49, 0, 0, 0)
  4896		case AMOVH:
  4897			return OPVCC(42, 0, 0, 0)
  4898		case AMOVHU:
  4899			return OPVCC(43, 0, 0, 0)
  4900		case AMOVHZ:
  4901			return OPVCC(40, 0, 0, 0)
  4902		case AMOVHZU:
  4903			return OPVCC(41, 0, 0, 0)
  4904		case AMOVMW:
  4905			return OPVCC(46, 0, 0, 0) /* lmw */
  4906		}
  4907	
  4908		c.ctxt.Diag("bad load opcode %v", a)
  4909		return 0
  4910	}
  4911	
  4912	/*
  4913	 * indexed load a(b),d
  4914	 */
  4915	func (c *ctxt9) oploadx(a obj.As) uint32 {
  4916		switch a {
  4917		case AMOVWZ:
  4918			return OPVCC(31, 23, 0, 0) /* lwzx */
  4919		case AMOVWZU:
  4920			return OPVCC(31, 55, 0, 0) /* lwzux */
  4921		case AMOVW:
  4922			return OPVCC(31, 341, 0, 0) /* lwax */
  4923		case AMOVWU:
  4924			return OPVCC(31, 373, 0, 0) /* lwaux */
  4925	
  4926		case AMOVB, AMOVBZ:
  4927			return OPVCC(31, 87, 0, 0) /* lbzx */
  4928	
  4929		case AMOVBU, AMOVBZU:
  4930			return OPVCC(31, 119, 0, 0) /* lbzux */
  4931		case AFMOVD:
  4932			return OPVCC(31, 599, 0, 0) /* lfdx */
  4933		case AFMOVDU:
  4934			return OPVCC(31, 631, 0, 0) /*  lfdux */
  4935		case AFMOVS:
  4936			return OPVCC(31, 535, 0, 0) /* lfsx */
  4937		case AFMOVSU:
  4938			return OPVCC(31, 567, 0, 0) /* lfsux */
  4939		case AFMOVSX:
  4940			return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */
  4941		case AFMOVSZ:
  4942			return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */
  4943		case AMOVH:
  4944			return OPVCC(31, 343, 0, 0) /* lhax */
  4945		case AMOVHU:
  4946			return OPVCC(31, 375, 0, 0) /* lhaux */
  4947		case AMOVHBR:
  4948			return OPVCC(31, 790, 0, 0) /* lhbrx */
  4949		case AMOVWBR:
  4950			return OPVCC(31, 534, 0, 0) /* lwbrx */
  4951		case AMOVDBR:
  4952			return OPVCC(31, 532, 0, 0) /* ldbrx */
  4953		case AMOVHZ:
  4954			return OPVCC(31, 279, 0, 0) /* lhzx */
  4955		case AMOVHZU:
  4956			return OPVCC(31, 311, 0, 0) /* lhzux */
  4957		case AECIWX:
  4958			return OPVCC(31, 310, 0, 0) /* eciwx */
  4959		case ALBAR:
  4960			return OPVCC(31, 52, 0, 0) /* lbarx */
  4961		case ALHAR:
  4962			return OPVCC(31, 116, 0, 0) /* lharx */
  4963		case ALWAR:
  4964			return OPVCC(31, 20, 0, 0) /* lwarx */
  4965		case ALDAR:
  4966			return OPVCC(31, 84, 0, 0) /* ldarx */
  4967		case ALSW:
  4968			return OPVCC(31, 533, 0, 0) /* lswx */
  4969		case AMOVD:
  4970			return OPVCC(31, 21, 0, 0) /* ldx */
  4971		case AMOVDU:
  4972			return OPVCC(31, 53, 0, 0) /* ldux */
  4973		case ALDMX:
  4974			return OPVCC(31, 309, 0, 0) /* ldmx */
  4975	
  4976		/* Vector (VMX/Altivec) instructions */
  4977		/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  4978		/* are enabled starting at POWER6 (ISA 2.05). */
  4979		case ALVEBX:
  4980			return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */
  4981		case ALVEHX:
  4982			return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */
  4983		case ALVEWX:
  4984			return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */
  4985		case ALVX:
  4986			return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */
  4987		case ALVXL:
  4988			return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */
  4989		case ALVSL:
  4990			return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */
  4991		case ALVSR:
  4992			return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */
  4993			/* End of vector instructions */
  4994	
  4995		/* Vector scalar (VSX) instructions */
  4996		/* ISA 2.06 enables these for POWER7. */
  4997		case ALXVD2X:
  4998			return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */
  4999		case ALXVDSX:
  5000			return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */
  5001		case ALXVW4X:
  5002			return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */
  5003	
  5004		case ALXSDX:
  5005			return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */
  5006	
  5007		case ALXSIWAX:
  5008			return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */
  5009		case ALXSIWZX:
  5010			return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */
  5011			/* End of vector scalar instructions */
  5012	
  5013		}
  5014	
  5015		c.ctxt.Diag("bad loadx opcode %v", a)
  5016		return 0
  5017	}
  5018	
  5019	/*
  5020	 * store s,o(d)
  5021	 */
  5022	func (c *ctxt9) opstore(a obj.As) uint32 {
  5023		switch a {
  5024		case AMOVB, AMOVBZ:
  5025			return OPVCC(38, 0, 0, 0) /* stb */
  5026	
  5027		case AMOVBU, AMOVBZU:
  5028			return OPVCC(39, 0, 0, 0) /* stbu */
  5029		case AFMOVD:
  5030			return OPVCC(54, 0, 0, 0) /* stfd */
  5031		case AFMOVDU:
  5032			return OPVCC(55, 0, 0, 0) /* stfdu */
  5033		case AFMOVS:
  5034			return OPVCC(52, 0, 0, 0) /* stfs */
  5035		case AFMOVSU:
  5036			return OPVCC(53, 0, 0, 0) /* stfsu */
  5037	
  5038		case AMOVHZ, AMOVH:
  5039			return OPVCC(44, 0, 0, 0) /* sth */
  5040	
  5041		case AMOVHZU, AMOVHU:
  5042			return OPVCC(45, 0, 0, 0) /* sthu */
  5043		case AMOVMW:
  5044			return OPVCC(47, 0, 0, 0) /* stmw */
  5045		case ASTSW:
  5046			return OPVCC(31, 725, 0, 0) /* stswi */
  5047	
  5048		case AMOVWZ, AMOVW:
  5049			return OPVCC(36, 0, 0, 0) /* stw */
  5050	
  5051		case AMOVWZU, AMOVWU:
  5052			return OPVCC(37, 0, 0, 0) /* stwu */
  5053		case AMOVD:
  5054			return OPVCC(62, 0, 0, 0) /* std */
  5055		case AMOVDU:
  5056			return OPVCC(62, 0, 0, 1) /* stdu */
  5057		}
  5058	
  5059		c.ctxt.Diag("unknown store opcode %v", a)
  5060		return 0
  5061	}
  5062	
  5063	/*
  5064	 * indexed store s,a(b)
  5065	 */
  5066	func (c *ctxt9) opstorex(a obj.As) uint32 {
  5067		switch a {
  5068		case AMOVB, AMOVBZ:
  5069			return OPVCC(31, 215, 0, 0) /* stbx */
  5070	
  5071		case AMOVBU, AMOVBZU:
  5072			return OPVCC(31, 247, 0, 0) /* stbux */
  5073		case AFMOVD:
  5074			return OPVCC(31, 727, 0, 0) /* stfdx */
  5075		case AFMOVDU:
  5076			return OPVCC(31, 759, 0, 0) /* stfdux */
  5077		case AFMOVS:
  5078			return OPVCC(31, 663, 0, 0) /* stfsx */
  5079		case AFMOVSU:
  5080			return OPVCC(31, 695, 0, 0) /* stfsux */
  5081		case AFMOVSX:
  5082			return OPVCC(31, 983, 0, 0) /* stfiwx */
  5083	
  5084		case AMOVHZ, AMOVH:
  5085			return OPVCC(31, 407, 0, 0) /* sthx */
  5086		case AMOVHBR:
  5087			return OPVCC(31, 918, 0, 0) /* sthbrx */
  5088	
  5089		case AMOVHZU, AMOVHU:
  5090			return OPVCC(31, 439, 0, 0) /* sthux */
  5091	
  5092		case AMOVWZ, AMOVW:
  5093			return OPVCC(31, 151, 0, 0) /* stwx */
  5094	
  5095		case AMOVWZU, AMOVWU:
  5096			return OPVCC(31, 183, 0, 0) /* stwux */
  5097		case ASTSW:
  5098			return OPVCC(31, 661, 0, 0) /* stswx */
  5099		case AMOVWBR:
  5100			return OPVCC(31, 662, 0, 0) /* stwbrx */
  5101		case AMOVDBR:
  5102			return OPVCC(31, 660, 0, 0) /* stdbrx */
  5103		case ASTBCCC:
  5104			return OPVCC(31, 694, 0, 1) /* stbcx. */
  5105		case ASTWCCC:
  5106			return OPVCC(31, 150, 0, 1) /* stwcx. */
  5107		case ASTDCCC:
  5108			return OPVCC(31, 214, 0, 1) /* stwdx. */
  5109		case AECOWX:
  5110			return OPVCC(31, 438, 0, 0) /* ecowx */
  5111		case AMOVD:
  5112			return OPVCC(31, 149, 0, 0) /* stdx */
  5113		case AMOVDU:
  5114			return OPVCC(31, 181, 0, 0) /* stdux */
  5115	
  5116		/* Vector (VMX/Altivec) instructions */
  5117		/* ISA 2.03 enables these for PPC970. For POWERx processors, these */
  5118		/* are enabled starting at POWER6 (ISA 2.05). */
  5119		case ASTVEBX:
  5120			return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */
  5121		case ASTVEHX:
  5122			return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */
  5123		case ASTVEWX:
  5124			return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */
  5125		case ASTVX:
  5126			return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */
  5127		case ASTVXL:
  5128			return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */
  5129			/* End of vector instructions */
  5130	
  5131		/* Vector scalar (VSX) instructions */
  5132		/* ISA 2.06 enables these for POWER7. */
  5133		case ASTXVD2X:
  5134			return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */
  5135		case ASTXVW4X:
  5136			return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */
  5137	
  5138		case ASTXSDX:
  5139			return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */
  5140	
  5141		case ASTXSIWX:
  5142			return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */
  5143			/* End of vector scalar instructions */
  5144	
  5145		}
  5146	
  5147		c.ctxt.Diag("unknown storex opcode %v", a)
  5148		return 0
  5149	}
  5150	

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