Source file src/pkg/cmd/internal/obj/arm/a.out.go

     1	// Inferno utils/5c/5.out.h
     2	// https://bitbucket.org/inferno-os/inferno-os/src/default/utils/5c/5.out.h
     3	//
     4	//	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     5	//	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     6	//	Portions Copyright © 1997-1999 Vita Nuova Limited
     7	//	Portions Copyright © 2000-2007 Vita Nuova Holdings Limited (www.vitanuova.com)
     8	//	Portions Copyright © 2004,2006 Bruce Ellis
     9	//	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
    10	//	Revisions Copyright © 2000-2007 Lucent Technologies Inc. and others
    11	//	Portions Copyright © 2009 The Go Authors. All rights reserved.
    12	//
    13	// Permission is hereby granted, free of charge, to any person obtaining a copy
    14	// of this software and associated documentation files (the "Software"), to deal
    15	// in the Software without restriction, including without limitation the rights
    16	// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    17	// copies of the Software, and to permit persons to whom the Software is
    18	// furnished to do so, subject to the following conditions:
    19	//
    20	// The above copyright notice and this permission notice shall be included in
    21	// all copies or substantial portions of the Software.
    22	//
    23	// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    24	// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    25	// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    26	// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    27	// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    28	// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    29	// THE SOFTWARE.
    30	
    31	package arm
    32	
    33	import "cmd/internal/obj"
    34	
    35	//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p arm
    36	
    37	const (
    38		NSNAME = 8
    39		NSYM   = 50
    40		NREG   = 16
    41	)
    42	
    43	/* -1 disables use of REGARG */
    44	const (
    45		REGARG = -1
    46	)
    47	
    48	const (
    49		REG_R0 = obj.RBaseARM + iota // must be 16-aligned
    50		REG_R1
    51		REG_R2
    52		REG_R3
    53		REG_R4
    54		REG_R5
    55		REG_R6
    56		REG_R7
    57		REG_R8
    58		REG_R9
    59		REG_R10
    60		REG_R11
    61		REG_R12
    62		REG_R13
    63		REG_R14
    64		REG_R15
    65	
    66		REG_F0 // must be 16-aligned
    67		REG_F1
    68		REG_F2
    69		REG_F3
    70		REG_F4
    71		REG_F5
    72		REG_F6
    73		REG_F7
    74		REG_F8
    75		REG_F9
    76		REG_F10
    77		REG_F11
    78		REG_F12
    79		REG_F13
    80		REG_F14
    81		REG_F15
    82	
    83		REG_FPSR // must be 2-aligned
    84		REG_FPCR
    85	
    86		REG_CPSR // must be 2-aligned
    87		REG_SPSR
    88	
    89		REGRET = REG_R0
    90		/* compiler allocates R1 up as temps */
    91		/* compiler allocates register variables R3 up */
    92		/* compiler allocates external registers R10 down */
    93		REGEXT = REG_R10
    94		/* these two registers are declared in runtime.h */
    95		REGG = REGEXT - 0
    96		REGM = REGEXT - 1
    97	
    98		REGCTXT = REG_R7
    99		REGTMP  = REG_R11
   100		REGSP   = REG_R13
   101		REGLINK = REG_R14
   102		REGPC   = REG_R15
   103	
   104		NFREG = 16
   105		/* compiler allocates register variables F0 up */
   106		/* compiler allocates external registers F7 down */
   107		FREGRET = REG_F0
   108		FREGEXT = REG_F7
   109		FREGTMP = REG_F15
   110	)
   111	
   112	// http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040b/IHI0040B_aadwarf.pdf
   113	var ARMDWARFRegisters = map[int16]int16{}
   114	
   115	func init() {
   116		// f assigns dwarfregisters[from:to] = (base):(step*(to-from)+base)
   117		f := func(from, to, base, step int16) {
   118			for r := int16(from); r <= to; r++ {
   119				ARMDWARFRegisters[r] = step*(r-from) + base
   120			}
   121		}
   122		f(REG_R0, REG_R15, 0, 1)
   123		f(REG_F0, REG_F15, 64, 2) // Use d0 through D15, aka S0, S2, ..., S30
   124	}
   125	
   126	// Special registers, after subtracting obj.RBaseARM, bit 9 indicates
   127	// a special register and the low bits select the register.
   128	const (
   129		REG_SPECIAL = obj.RBaseARM + 1<<9 + iota
   130		REG_MB_SY
   131		REG_MB_ST
   132		REG_MB_ISH
   133		REG_MB_ISHST
   134		REG_MB_NSH
   135		REG_MB_NSHST
   136		REG_MB_OSH
   137		REG_MB_OSHST
   138	
   139		MAXREG
   140	)
   141	
   142	const (
   143		C_NONE = iota
   144		C_REG
   145		C_REGREG
   146		C_REGREG2
   147		C_REGLIST
   148		C_SHIFT     /* register shift R>>x */
   149		C_SHIFTADDR /* memory address with shifted offset R>>x(R) */
   150		C_FREG
   151		C_PSR
   152		C_FCR
   153		C_SPR /* REG_MB_SY */
   154	
   155		C_RCON   /* 0xff rotated */
   156		C_NCON   /* ~RCON */
   157		C_RCON2A /* OR of two disjoint C_RCON constants */
   158		C_RCON2S /* subtraction of two disjoint C_RCON constants */
   159		C_SCON   /* 0xffff */
   160		C_LCON
   161		C_LCONADDR
   162		C_ZFCON
   163		C_SFCON
   164		C_LFCON
   165	
   166		C_RACON
   167		C_LACON
   168	
   169		C_SBRA
   170		C_LBRA
   171	
   172		C_HAUTO  /* halfword insn offset (-0xff to 0xff) */
   173		C_FAUTO  /* float insn offset (0 to 0x3fc, word aligned) */
   174		C_HFAUTO /* both H and F */
   175		C_SAUTO  /* -0xfff to 0xfff */
   176		C_LAUTO
   177	
   178		C_HOREG
   179		C_FOREG
   180		C_HFOREG
   181		C_SOREG
   182		C_ROREG
   183		C_SROREG /* both nil and R */
   184		C_LOREG
   185	
   186		C_PC
   187		C_SP
   188		C_HREG
   189	
   190		C_ADDR /* reference to relocatable address */
   191	
   192		// TLS "var" in local exec mode: will become a constant offset from
   193		// thread local base that is ultimately chosen by the program linker.
   194		C_TLS_LE
   195	
   196		// TLS "var" in initial exec mode: will become a memory address (chosen
   197		// by the program linker) that the dynamic linker will fill with the
   198		// offset from the thread local base.
   199		C_TLS_IE
   200	
   201		C_TEXTSIZE
   202	
   203		C_GOK
   204	
   205		C_NCLASS /* must be the last */
   206	)
   207	
   208	const (
   209		AAND = obj.ABaseARM + obj.A_ARCHSPECIFIC + iota
   210		AEOR
   211		ASUB
   212		ARSB
   213		AADD
   214		AADC
   215		ASBC
   216		ARSC
   217		ATST
   218		ATEQ
   219		ACMP
   220		ACMN
   221		AORR
   222		ABIC
   223	
   224		AMVN
   225	
   226		/*
   227		 * Do not reorder or fragment the conditional branch
   228		 * opcodes, or the predication code will break
   229		 */
   230		ABEQ
   231		ABNE
   232		ABCS
   233		ABHS
   234		ABCC
   235		ABLO
   236		ABMI
   237		ABPL
   238		ABVS
   239		ABVC
   240		ABHI
   241		ABLS
   242		ABGE
   243		ABLT
   244		ABGT
   245		ABLE
   246	
   247		AMOVWD
   248		AMOVWF
   249		AMOVDW
   250		AMOVFW
   251		AMOVFD
   252		AMOVDF
   253		AMOVF
   254		AMOVD
   255	
   256		ACMPF
   257		ACMPD
   258		AADDF
   259		AADDD
   260		ASUBF
   261		ASUBD
   262		AMULF
   263		AMULD
   264		ANMULF
   265		ANMULD
   266		AMULAF
   267		AMULAD
   268		ANMULAF
   269		ANMULAD
   270		AMULSF
   271		AMULSD
   272		ANMULSF
   273		ANMULSD
   274		AFMULAF
   275		AFMULAD
   276		AFNMULAF
   277		AFNMULAD
   278		AFMULSF
   279		AFMULSD
   280		AFNMULSF
   281		AFNMULSD
   282		ADIVF
   283		ADIVD
   284		ASQRTF
   285		ASQRTD
   286		AABSF
   287		AABSD
   288		ANEGF
   289		ANEGD
   290	
   291		ASRL
   292		ASRA
   293		ASLL
   294		AMULU
   295		ADIVU
   296		AMUL
   297		AMMUL
   298		ADIV
   299		AMOD
   300		AMODU
   301		ADIVHW
   302		ADIVUHW
   303	
   304		AMOVB
   305		AMOVBS
   306		AMOVBU
   307		AMOVH
   308		AMOVHS
   309		AMOVHU
   310		AMOVW
   311		AMOVM
   312		ASWPBU
   313		ASWPW
   314	
   315		ARFE
   316		ASWI
   317		AMULA
   318		AMULS
   319		AMMULA
   320		AMMULS
   321	
   322		AWORD
   323	
   324		AMULL
   325		AMULAL
   326		AMULLU
   327		AMULALU
   328	
   329		ABX
   330		ABXRET
   331		ADWORD
   332	
   333		ALDREX
   334		ASTREX
   335		ALDREXD
   336		ASTREXD
   337	
   338		ADMB
   339	
   340		APLD
   341	
   342		ACLZ
   343		AREV
   344		AREV16
   345		AREVSH
   346		ARBIT
   347	
   348		AXTAB
   349		AXTAH
   350		AXTABU
   351		AXTAHU
   352	
   353		ABFX
   354		ABFXU
   355		ABFC
   356		ABFI
   357	
   358		AMULWT
   359		AMULWB
   360		AMULBB
   361		AMULAWT
   362		AMULAWB
   363		AMULABB
   364	
   365		ADATABUNDLE
   366		ADATABUNDLEEND
   367	
   368		AMRC // MRC/MCR
   369	
   370		ALAST
   371	
   372		// aliases
   373		AB  = obj.AJMP
   374		ABL = obj.ACALL
   375	)
   376	
   377	/* scond byte */
   378	const (
   379		C_SCOND = (1 << 4) - 1
   380		C_SBIT  = 1 << 4
   381		C_PBIT  = 1 << 5
   382		C_WBIT  = 1 << 6
   383		C_FBIT  = 1 << 7 /* psr flags-only */
   384		C_UBIT  = 1 << 7 /* up bit, unsigned bit */
   385	
   386		// These constants are the ARM condition codes encodings,
   387		// XORed with 14 so that C_SCOND_NONE has value 0,
   388		// so that a zeroed Prog.scond means "always execute".
   389		C_SCOND_XOR = 14
   390	
   391		C_SCOND_EQ   = 0 ^ C_SCOND_XOR
   392		C_SCOND_NE   = 1 ^ C_SCOND_XOR
   393		C_SCOND_HS   = 2 ^ C_SCOND_XOR
   394		C_SCOND_LO   = 3 ^ C_SCOND_XOR
   395		C_SCOND_MI   = 4 ^ C_SCOND_XOR
   396		C_SCOND_PL   = 5 ^ C_SCOND_XOR
   397		C_SCOND_VS   = 6 ^ C_SCOND_XOR
   398		C_SCOND_VC   = 7 ^ C_SCOND_XOR
   399		C_SCOND_HI   = 8 ^ C_SCOND_XOR
   400		C_SCOND_LS   = 9 ^ C_SCOND_XOR
   401		C_SCOND_GE   = 10 ^ C_SCOND_XOR
   402		C_SCOND_LT   = 11 ^ C_SCOND_XOR
   403		C_SCOND_GT   = 12 ^ C_SCOND_XOR
   404		C_SCOND_LE   = 13 ^ C_SCOND_XOR
   405		C_SCOND_NONE = 14 ^ C_SCOND_XOR
   406		C_SCOND_NV   = 15 ^ C_SCOND_XOR
   407	
   408		/* D_SHIFT type */
   409		SHIFT_LL = 0 << 5
   410		SHIFT_LR = 1 << 5
   411		SHIFT_AR = 2 << 5
   412		SHIFT_RR = 3 << 5
   413	)
   414	

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